Lines Matching defs:gmc
52 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
53 uint32_t pde0_page_shift = adev->gmc.vmid0_page_table_block_size + 21;
66 r = amdgpu_bo_create(adev, &bp, &adev->gmc.pdb0_bo);
70 r = amdgpu_bo_reserve(adev->gmc.pdb0_bo, false);
74 r = amdgpu_bo_pin(adev->gmc.pdb0_bo, AMDGPU_GEM_DOMAIN_VRAM);
77 r = amdgpu_bo_kmap(adev->gmc.pdb0_bo, &adev->gmc.ptr_pdb0);
81 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
85 amdgpu_bo_unpin(adev->gmc.pdb0_bo);
87 amdgpu_bo_unreserve(adev->gmc.pdb0_bo);
89 amdgpu_bo_unref(&adev->gmc.pdb0_bo);
186 if (bo->ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
189 return adev->gmc.agp_start + bo->ttm->dma_address[0];
276 u64 max_mc_address = min(adev->gmc.mc_mask, AMDGPU_GMC_HOLE_START - 1);
377 struct amdgpu_gmc *gmc = &adev->gmc;
389 if (gmc->fault_ring[gmc->last_fault].timestamp >= stamp)
394 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
415 fault = &gmc->fault_ring[fault->next];
423 fault = &gmc->fault_ring[gmc->last_fault];
428 fault->next = gmc->fault_hash[hash].idx;
429 gmc->fault_hash[hash].idx = gmc->last_fault++;
446 struct amdgpu_gmc *gmc = &adev->gmc;
464 fault = &gmc->fault_ring[gmc->fault_hash[hash].idx];
476 fault = &gmc->fault_ring[fault->next];
598 adev->gmc.tmz_enabled = false;
602 adev->gmc.tmz_enabled = true;
624 adev->gmc.tmz_enabled = false;
628 adev->gmc.tmz_enabled = true;
634 adev->gmc.tmz_enabled = false;
650 struct amdgpu_gmc *gmc = &adev->gmc;
659 gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry;
754 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
788 u64 vram_size = adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
789 u64 pde0_page_size = (1ULL<<adev->gmc.vmid0_page_table_block_size)<<21;
791 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
802 flags |= AMDGPU_PTE_FRAG((adev->gmc.vmid0_page_table_block_size + 9*1));
809 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, vram_addr, flags);
818 amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);
831 return mc_addr - adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
855 return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base;
918 mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev);
943 if (!adev->gmc.gmc_funcs->query_mem_partition_mode)