Lines Matching defs:queue
43 int pipe, int queue)
50 bit += queue;
56 int *mec, int *pipe, int *queue)
58 *queue = bit % adev->gfx.mec.num_queue_per_pipe;
67 int xcc_id, int mec, int pipe, int queue)
69 return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
74 int me, int pipe, int queue)
81 bit += queue;
87 int *me, int *pipe, int *queue)
89 *queue = bit % adev->gfx.me.num_queue_per_pipe;
97 int me, int pipe, int queue)
99 return test_bit(amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue),
177 int queue = ring->queue;
180 /* Policy: use pipe1 queue0 as high priority graphics queue if we
184 adev->gfx.num_gfx_rings > 1 && pipe == 1 && queue == 0) {
188 bit = amdgpu_gfx_me_queue_to_bit(adev, me, pipe, queue);
199 /* Policy: use 1st queue as high priority compute queue if we
200 * have more than one compute queue.
211 int i, j, queue, pipe;
224 queue = (i / adev->gfx.mec.num_pipe_per_mec) %
227 set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
240 dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
247 int i, queue, pipe;
253 /* policy: amdgpu owns the first queue per pipe at this stage
257 queue = (i / adev->gfx.me.num_pipe_per_me) %
260 set_bit(pipe * adev->gfx.me.num_queue_per_pipe + queue,
277 int mec, pipe, queue;
287 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
291 * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN
292 * only can be issued on queue 0.
294 if ((mec == 1 && pipe > 1) || queue != 0)
299 ring->queue = queue;
304 dev_err(adev->dev, "Failed to find a queue for KIQ\n");
333 snprintf(ring->name, sizeof(ring->name), "kiq_%d.%d.%d.%d", xcc_id, ring->me, ring->pipe, ring->queue);
380 /* create MQD for each compute/gfx queue */
571 int mec, pipe, queue;
574 amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
576 set_resource_bit = mec * 4 * 8 + pipe * 8 + queue;
607 kiq_ring->queue);
1066 dev_warn(adev->dev, "set kernel compute queue number to 8 due to invalid parameter provided by user\n");