Lines Matching defs:afb
721 static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)
723 struct amdgpu_device *adev = drm_to_adev(afb->base.dev);
731 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) {
734 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE);
743 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B);
786 if (!has_xor && afb->base.format->cpp[0] != 4)
825 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) |
832 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0;
853 afb->base.offsets[1] = dcc_offset * 256 + afb->base.offsets[0];
854 afb->base.pitches[1] =
855 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1;
865 if (extract_render_dcc_offset(adev, afb->base.obj[0],
868 render_dcc_offset != afb->base.offsets[1] &&
873 afb->base.offsets[2] = render_dcc_offset;
889 dcc_block_bits -= ilog2(afb->base.format->cpp[0]);
890 afb->base.pitches[2] = ALIGN(afb->base.width,
893 format_info = amdgpu_lookup_format_info(afb->base.format->format,
898 afb->base.format = format_info;
902 afb->base.modifier = modifier;
903 afb->base.flags |= DRM_MODE_FB_MODIFIERS;
908 static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb)
912 if (AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) == 1) /* LINEAR_ALIGNED */
915 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
921 drm_dbg_kms(afb->base.dev,