Lines Matching defs:tmp_adev
5049 struct amdgpu_device *tmp_adev = NULL;
5055 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5057 amdgpu_reset_reg_dumps(tmp_adev);
5060 r = amdgpu_reset_perform_reset(tmp_adev, reset_context);
5081 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5083 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5084 tmp_adev->gmc.xgmi.pending_reset = false;
5085 if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work))
5088 r = amdgpu_asic_reset(tmp_adev);
5091 dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s",
5092 r, adev_to_drm(tmp_adev)->unique);
5099 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5100 if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {
5101 flush_work(&tmp_adev->xgmi_reset_work);
5102 r = tmp_adev->asic_reset_res;
5111 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5112 if (tmp_adev->mmhub.ras && tmp_adev->mmhub.ras->ras_block.hw_ops &&
5113 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count)
5114 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev);
5126 list_for_each_entry(tmp_adev, device_list_handle, reset_list)
5127 amdgpu_device_ip_resume_phase1(tmp_adev);
5132 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5135 r = amdgpu_device_asic_init(tmp_adev);
5137 dev_warn(tmp_adev->dev, "asic atom init failed!");
5139 dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n");
5141 r = amdgpu_device_ip_resume_phase1(tmp_adev);
5145 vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
5147 tmp_adev->reset_vram_lost = vram_lost;
5148 memset(&tmp_adev->reset_task_info, 0,
5149 sizeof(tmp_adev->reset_task_info));
5151 tmp_adev->reset_task_info =
5153 amdgpu_reset_capture_coredumpm(tmp_adev);
5157 amdgpu_inc_vram_lost(tmp_adev);
5160 r = amdgpu_device_fw_loading(tmp_adev);
5164 r = amdgpu_device_ip_resume_phase2(tmp_adev);
5168 r = amdgpu_device_ip_resume_phase3(tmp_adev);
5173 amdgpu_device_fill_reset_magic(tmp_adev);
5179 amdgpu_register_gpu_instance(tmp_adev);
5182 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5183 amdgpu_xgmi_add_device(tmp_adev);
5185 r = amdgpu_device_ip_late_init(tmp_adev);
5189 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false);
5201 if (!amdgpu_ras_eeprom_check_err_threshold(tmp_adev)) {
5203 amdgpu_ras_resume(tmp_adev);
5211 tmp_adev->gmc.xgmi.num_physical_nodes > 1)
5213 reset_context->hive, tmp_adev);
5219 amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
5220 r = amdgpu_ib_ring_tests(tmp_adev);
5222 dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r);
5230 r = amdgpu_device_recover_vram(tmp_adev);
5232 tmp_adev->asic_reset_res = r;
5374 struct amdgpu_device *tmp_adev = NULL;
5422 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) {
5423 list_add_tail(&tmp_adev->reset_list, &device_list);
5425 tmp_adev->shutdown = true;
5436 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5438 amdgpu_device_lock_reset_domain(tmp_adev->reset_domain);
5441 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5443 amdgpu_device_set_mp1_state(tmp_adev);
5455 if (!amdgpu_device_suspend_display_audio(tmp_adev))
5458 amdgpu_ras_set_error_query_ready(tmp_adev, false);
5460 cancel_delayed_work_sync(&tmp_adev->delayed_init_work);
5462 if (!amdgpu_sriov_vf(tmp_adev))
5463 amdgpu_amdkfd_pre_reset(tmp_adev);
5469 amdgpu_unregister_gpu_instance(tmp_adev);
5471 drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true);
5475 amdgpu_device_ip_need_full_reset(tmp_adev))
5476 amdgpu_ras_suspend(tmp_adev);
5479 struct amdgpu_ring *ring = tmp_adev->rings[i];
5489 atomic_inc(&tmp_adev->gpu_reset_counter);
5508 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5511 amdgpu_device_smu_fini_early(tmp_adev);
5513 r = amdgpu_device_pre_asic_reset(tmp_adev, reset_context);
5516 dev_err(tmp_adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
5517 r, adev_to_drm(tmp_adev)->unique);
5518 tmp_adev->asic_reset_res = r;
5525 amdgpu_device_stop_pending_resets(tmp_adev);
5551 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5554 struct amdgpu_ring *ring = tmp_adev->rings[i];
5563 amdgpu_mes_self_test(tmp_adev);
5565 if (!drm_drv_uses_atomic_modeset(adev_to_drm(tmp_adev)) && !job_signaled)
5566 drm_helper_resume_force_mode(adev_to_drm(tmp_adev));
5568 if (tmp_adev->asic_reset_res)
5569 r = tmp_adev->asic_reset_res;
5571 tmp_adev->asic_reset_res = 0;
5575 dev_info(tmp_adev->dev, "GPU reset(%d) failed\n", atomic_read(&tmp_adev->gpu_reset_counter));
5576 amdgpu_vf_error_put(tmp_adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
5578 dev_info(tmp_adev->dev, "GPU reset(%d) succeeded!\n", atomic_read(&tmp_adev->gpu_reset_counter));
5579 if (amdgpu_acpi_smart_shift_update(adev_to_drm(tmp_adev), AMDGPU_SS_DEV_D0))
5585 list_for_each_entry(tmp_adev, device_list_handle, reset_list) {
5587 if (!need_emergency_restart && !amdgpu_sriov_vf(tmp_adev))
5588 amdgpu_amdkfd_post_reset(tmp_adev);
5597 amdgpu_device_resume_display_audio(tmp_adev);
5599 amdgpu_device_unset_mp1_state(tmp_adev);
5601 amdgpu_ras_set_error_query_ready(tmp_adev, true);
5605 tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device,
5607 amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain);