Lines Matching defs:adev
74 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
76 bool vf = amdgpu_sriov_vf(adev);
81 adev->kfd.dev = kgd2kfd_probe(adev, vf);
88 * @adev: amdgpu_device pointer
97 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
106 if (adev->enable_mes) {
113 *aperture_base = adev->doorbell.base;
116 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells *
118 *aperture_base = adev->doorbell.base;
119 *aperture_size = adev->doorbell.size;
120 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32);
131 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
139 reset_context.reset_req_dev = adev;
142 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
145 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
152 if (adev->kfd.dev) {
156 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
157 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
158 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
159 .gpuvm_size = min(adev->vm_manager.max_pfn
162 .drm_render_minor = adev_to_drm(adev)->render->index,
163 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
164 .enable_mes = adev->enable_mes,
171 adev->gfx.mec_bitmap[0].queue_bitmap,
178 * adev->gfx.mec.num_pipe_per_mec
179 * adev->gfx.mec.num_queue_per_pipe;
183 amdgpu_doorbell_get_kfd_info(adev,
196 if (adev->asic_type >= CHIP_VEGA10) {
198 adev->doorbell_index.first_non_cp;
200 adev->doorbell_index.last_non_cp;
203 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
206 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
208 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
212 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
214 if (adev->kfd.dev) {
215 kgd2kfd_device_exit(adev->kfd.dev);
216 adev->kfd.dev = NULL;
217 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size;
221 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
224 if (adev->kfd.dev)
225 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
228 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
230 if (adev->kfd.dev)
231 kgd2kfd_suspend(adev->kfd.dev, run_pm);
234 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
238 if (adev->kfd.dev)
239 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
244 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
248 if (adev->kfd.dev)
249 r = kgd2kfd_pre_reset(adev->kfd.dev);
254 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
258 if (adev->kfd.dev)
259 r = kgd2kfd_post_reset(adev->kfd.dev);
264 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
266 if (amdgpu_device_should_recover_gpu(adev))
267 amdgpu_reset_domain_schedule(adev->reset_domain,
268 &adev->kfd.reset_work);
271 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
292 r = amdgpu_bo_create(adev, &bp, &bo);
294 dev_err(adev->dev,
302 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
308 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
314 dev_err(adev->dev, "%p bind failed\n", bo);
320 dev_err(adev->dev,
343 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj)
354 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
371 r = amdgpu_bo_create_user(adev, &bp, &ubo);
373 dev_err(adev->dev,
383 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
390 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
395 return adev->gfx.pfp_fw_version;
398 return adev->gfx.me_fw_version;
401 return adev->gfx.ce_fw_version;
404 return adev->gfx.mec_fw_version;
407 return adev->gfx.mec2_fw_version;
410 return adev->gfx.rlc_fw_version;
413 return adev->sdma.instance[0].fw_version;
416 return adev->sdma.instance[1].fw_version;
425 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
432 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size)
434 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
437 KFD_XCP_MEMORY_SIZE(adev, xcp->id);
439 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
440 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
441 adev->gmc.visible_vram_size;
443 mem_info->vram_width = adev->gmc.vram_width;
446 &adev->gmc.aper_base,
450 if (adev->pm.dpm_enabled) {
454 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
459 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
461 if (adev->gfx.funcs->get_gpu_clock_counter)
462 return adev->gfx.funcs->get_gpu_clock_counter(adev);
466 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
469 if (adev->pm.dpm_enabled)
470 return amdgpu_dpm_get_sclk(adev, false) / 100;
475 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info)
477 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
487 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
488 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
489 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
497 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
518 if (obj->dev->driver != adev_to_drm(adev)->driver)
522 adev = drm_to_adev(obj->dev);
531 *dmabuf_adev = adev;
557 struct amdgpu_device *adev = dst;
558 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
562 adev->gmc.xgmi.physical_node_id,
573 struct amdgpu_device *adev = dst, *peer_adev;
576 if (adev->asic_type != CHIP_ALDEBARAN)
583 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
586 adev->gmc.xgmi.physical_node_id,
595 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
597 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
598 fls(adev->pm.pcie_mlw_mask)) - 1;
599 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
601 fls(adev->pm.pcie_gen_mask &
652 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
665 ring = &adev->gfx.compute_ring[0];
668 ring = &adev->sdma.instance[0].ring;
671 ring = &adev->sdma.instance[1].ring;
679 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job);
710 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
715 if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) {
717 amdgpu_gfx_off_ctrl(adev, idle);
719 amdgpu_dpm_switch_power_profile(adev,
724 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
726 if (adev->kfd.dev)
727 return vmid >= adev->vm_manager.first_kfd_vmid;
732 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
735 if (adev->family == AMDGPU_FAMILY_AI) {
738 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS)
739 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
741 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0);
747 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
754 if (adev->family == AMDGPU_FAMILY_AI ||
755 adev->family == AMDGPU_FAMILY_RV)
758 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub, inst);
761 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
763 return adev->have_atomics_support;
766 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev)
768 amdgpu_device_flush_hdp(adev, NULL);
771 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
773 amdgpu_umc_poison_handler(adev, reset);
776 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
782 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih);
787 amdgpu_amdkfd_interrupt(adev, payload);
792 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
794 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status)
795 return adev->gfx.ras->query_utcl2_poison_status(adev);
800 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev)
805 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev)
811 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id)
814 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id);
816 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) {
817 tmp = adev->gmc.mem_partitions[mem_id].size;
818 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition);
821 return adev->gmc.real_vram_size;
825 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
828 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];
861 if (kiq_ring->sched.ready && !adev->job_hang)