43  * - base/limit registers (on 0x0f, 0x10, 0x11)
44  * - extended base/limit registers (on 0x10)
49  * base/limit registers use bits [31..16] to indicate address [39..24]
50  * extended base/limit registers use bits [7..0] to indicate address [47..40]
51  * base/limit addresses need to be shifted <<24 for memory address
52  * extended base/limit addresses need to be shifted <<40 for memory address
85  * - limit contains node selection bitmask [10..8] (on 0x0f, 0x10)
86  * - limit contains destination node [2..0] (on 0x0f, 0x10)
88 #define AMAS_DST_NODE(base, limit)	((limit) & 0x07)  argument
89 #define AMAS_INTL_ENABLE(base, limit)	(((base) >> 8) & 0x07)  argument
90 #define AMAS_INTL_SELECTOR(base, limit)	(((limit) >> 8) & 0x07)  argument
234 	pcireg_t base, ebase, limit, elimit;  in amas_get_pagerange()  local
249 	limit = pci_conf_read(amas->pa_pc, amas->pa_tag,  in amas_get_pagerange()
252 	limit_addr = AMAS_REG_BL_ADDR(limit);  in amas_get_pagerange()
278 	KASSERT(node == AMAS_DST_NODE(base, limit));  in amas_get_pagerange()