Lines Matching full:control
38 #define SPEAKER_CONTROL 0x61 /* W PC speaker Control register */
39 #define SPEAKER_CONTROL_GHOST 0x738B /* R W PC speaker Control ghost register */
40 #define SPEAKER_TIMER_CONTROL 0x43 /* W PC speaker Timer control register */
41 #define SPEAKER_TIMER_CONTROL_GHOST 0x778B /* R W PC speaker Timer control register ghost */
45 #define WARM_BOOT 0x41 /* W Control Used to detect system warm boot */
46 #define WARM_BOOT_GHOST 0x7789 /* ? W Control Use to get the card to fake warm boot */
47 #define MASTER_DECODE 0x9A01 /* W Control Address >> 2 of card base address */
49 #define WAIT_STATE 0xBF88 /* R W Control Four-bit bus wait-state count (~140ns ea.) */
50 #define BOARD_REV_ID 0x2789 /* R Control Extended Board Revision ID */
52 #define SYSTEM_CONFIGURATION_1 0x8388 /* R W Control */
58 #define S_C_1_FORCE_EXT_RESET 0x40 /* R W Control Force external reset */
59 #define S_C_1_FORCE_INT_RESET 0x80 /* R W Control Force internal reset */
60 #define SYSTEM_CONFIGURATION_2 0x8389 /* R W Control */
63 #define SYSTEM_CONFIGURATION_3 0x838A /* R W Control */
65 #define SYSTEM_CONFIGURATION_4 0x838B /* R W Control CD-ROM interface controls */
67 #define IO_CONFIGURATION_1 0xF388 /* R W Control */
68 #define I_C_1_BOOT_RESET_ENABLE 0x80 /* R W Control 1=reset board on warm boot, 0=don't */
69 #define IO_CONFIGURATION_2 0xF389 /* R W Control */
71 #define IO_CONFIGURATION_3 0xF38A /* R W Control */
74 #define COMPATIBILITY_ENABLE 0xF788 /* R W Control */
80 #define EMULATION_ADDRESS 0xF789 /* R W Control */
88 #define OPERATION_MODE_1 0xEF8B /* R Control */
92 #define OPERATION_MODE_2 0xFF8B /* R Control */
94 #define O_M_2_BUS_TIMING 0x10 /* R Control 1=AT bus timing, 0=XT bus timing */
95 #define O_M_2_BOARD_REVISION 0xe0 /* R Control Board revision */
97 #define INTERRUPT_MASK 0x0B8B /* R W Control */
103 #define I_M_BOARD_REV 0xE0 /* R Control Board revision */
105 #define INTERRUPT_STATUS 0x0B89 /* R W Control */
112 #define I_S_RESET_ACTIVE 0x40 /* R W Control Reset is active (Timed pulse not finished) */
115 #define FILTER_FREQUENCY 0x0B8A /* R W Control */
155 char O_M_1_to_card[] = /* R W Control Translate (OM1 & 0x0f) to card type */
163 extern char O_M_1_to_card[]; /* R W Control Translate (OM1 & 0x0f) to card type */
178 #define P_M_MV508_MASTER_A 0x01 /* W Mixer MVD508 Master volume control A (output) */
179 #define P_M_MV508_MASTER_B 0x02 /* W Mixer MVD508 Master volume control B (DSP input) */
180 #define P_M_MV508_BASS 0x03 /* W Mixer MVD508 Bass control */
181 #define P_M_MV508_TREBLE 0x04 /* W Mixer MVD508 Treble control */
182 #define P_M_MV508_MODE 0x05 /* W Mixer MVD508 Master mode control */
184 #define P_M_MV508_LOUDNESS 0x04 /* W Mixer MVD508 Mode control - Loudness filter */
185 #define P_M_MV508_ENHANCE_NONE 0x00 /* W Mixer MVD508 Mode control - No stereo enhancement */
186 #define P_M_MV508_ENHANCE_40 0x01 /* W Mixer MVD508 Mode control - 40% stereo enhancement */
187 #define P_M_MV508_ENHANCE_60 0x02 /* W Mixer MVD508 Mode control - 60% stereo enhancement */
188 #define P_M_MV508_ENHANCE_80 0x03 /* W Mixer MVD508 Mode control - 80% stereo enhancement */
199 #define SERIAL_MIXER 0xB88 /* R W Control Serial mixer control (used other ways) */
206 #define PCM_CONTROL 0xF8A /* R W PCM PCM Control Register */
219 #define SAMPLE_COUNTER_CONTROL 0x138B /* R W PCM Sample counter control register */
233 #define MIDI_CONTROL 0x178b /* R W MIDI Midi control register */