Lines Matching defs:sc
189 struct xl_softc *sc = (struct xl_softc *)self;
190 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
195 xl_stop(sc);
199 xl_init(sc);
203 xl_wol_power(sc);
219 xl_wait(struct xl_softc *sc)
224 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
229 printf("%s: command never completed!\n", sc->sc_dev.dv_xname);
242 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
243 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x))
246 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \
247 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x))
253 xl_mii_sync(struct xl_softc *sc)
274 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt)
296 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame)
316 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0);
322 xl_mii_sync(sc);
327 xl_mii_send(sc, frame->mii_stdelim, 2);
328 xl_mii_send(sc, frame->mii_opcode, 2);
329 xl_mii_send(sc, frame->mii_phyaddr, 5);
330 xl_mii_send(sc, frame->mii_regaddr, 5);
341 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA;
359 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA)
381 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame)
405 xl_mii_sync(sc);
407 xl_mii_send(sc, frame->mii_stdelim, 2);
408 xl_mii_send(sc, frame->mii_opcode, 2);
409 xl_mii_send(sc, frame->mii_phyaddr, 5);
410 xl_mii_send(sc, frame->mii_regaddr, 5);
411 xl_mii_send(sc, frame->mii_turnaround, 2);
412 xl_mii_send(sc, frame->mii_data, 16);
431 struct xl_softc *sc = (struct xl_softc *)self;
434 if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)
441 xl_mii_readreg(sc, &frame);
449 struct xl_softc *sc = (struct xl_softc *)self;
452 if (!(sc->xl_flags & XL_FLAG_PHYOK) && phy != 24)
461 xl_mii_writereg(sc, &frame);
467 struct xl_softc *sc = (struct xl_softc *)self;
469 xl_setcfg(sc);
473 if ((sc->sc_mii.mii_media_active & IFM_GMASK) == IFM_FDX)
474 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
476 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
477 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
485 xl_eeprom_wait(struct xl_softc *sc)
490 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
497 printf("%s: eeprom failed to come ready\n", sc->sc_dev.dv_xname);
509 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
521 if (xl_eeprom_wait(sc))
524 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
528 if (sc->xl_flags & XL_FLAG_8BITROM)
529 CSR_WRITE_2(sc, XL_W0_EE_CMD,
532 CSR_WRITE_2(sc, XL_W0_EE_CMD,
534 err = xl_eeprom_wait(sc);
537 word = CSR_READ_2(sc, XL_W0_EE_DATA);
549 xl_iff(struct xl_softc *sc)
551 if (sc->xl_type == XL_TYPE_905B)
552 xl_iff_905b(sc);
554 xl_iff_90x(sc);
562 xl_iff_90x(struct xl_softc *sc)
564 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
565 struct arpcom *ac = &sc->sc_arpcom;
570 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
589 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT | rxfilt);
598 xl_iff_905b(struct xl_softc *sc)
600 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
601 struct arpcom *ac = &sc->sc_arpcom;
609 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
632 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i);
639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH |
646 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT | rxfilt);
652 xl_setcfg(struct xl_softc *sc)
657 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
659 if (sc->xl_media & XL_MEDIAOPT_MII ||
660 sc->xl_media & XL_MEDIAOPT_BT4)
662 if (sc->xl_media & XL_MEDIAOPT_BTX)
665 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
666 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
670 xl_setmode(struct xl_softc *sc, uint64_t media)
672 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
677 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
679 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
681 if (sc->xl_media & XL_MEDIAOPT_BT) {
684 sc->xl_xcvr = XL_XCVR_10BT;
693 if (sc->xl_media & XL_MEDIAOPT_BFX) {
696 sc->xl_xcvr = XL_XCVR_100BFX;
704 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
707 sc->xl_xcvr = XL_XCVR_AUI;
716 sc->xl_xcvr = XL_XCVR_AUI;
725 if (sc->xl_media & XL_MEDIAOPT_BNC) {
728 sc->xl_xcvr = XL_XCVR_COAX;
740 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
743 CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
744 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
748 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
750 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
751 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
753 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
759 xl_reset(struct xl_softc *sc)
764 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
765 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
778 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
783 printf("%s: reset didn't complete\n", sc->sc_dev.dv_xname);
791 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
793 xl_wait(sc);
794 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
795 xl_wait(sc);
797 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
798 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
800 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, CSR_READ_2(sc,
802 | ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR)?XL_RESETOPT_INVERT_LED:0)
803 | ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR)?XL_RESETOPT_INVERT_MII:0)
824 xl_mediacheck(struct xl_softc *sc)
832 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
837 if (sc->xl_xcvr <= XL_XCVR_AUTO)
841 "in EEPROM (%x)\n", sc->sc_dev.dv_xname, sc->xl_xcvr);
843 "on card type\n", sc->sc_dev.dv_xname);
846 if (sc->xl_type == XL_TYPE_905B &&
847 sc->xl_media & XL_MEDIAOPT_10FL)
850 "the media options register!!\n", sc->sc_dev.dv_xname);
852 "your adapter or system\n", sc->sc_dev.dv_xname);
854 "should probably consult your vendor\n", sc->sc_dev.dv_xname);
857 xl_choose_xcvr(sc, 1);
861 xl_choose_xcvr(struct xl_softc *sc, int verbose)
870 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
875 sc->xl_media = XL_MEDIAOPT_BT;
876 sc->xl_xcvr = XL_XCVR_10BT;
879 sc->sc_dev.dv_xname);
883 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
884 sc->xl_xcvr = XL_XCVR_10BT;
887 sc->sc_dev.dv_xname);
890 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
891 sc->xl_xcvr = XL_XCVR_10BT;
893 printf("%s: guessing TPC (BNC/TP)\n", sc->sc_dev.dv_xname);
896 sc->xl_media = XL_MEDIAOPT_10FL;
897 sc->xl_xcvr = XL_XCVR_AUI;
899 printf("%s: guessing 10baseFL\n", sc->sc_dev.dv_xname);
912 sc->xl_media = XL_MEDIAOPT_MII;
913 sc->xl_xcvr = XL_XCVR_MII;
915 printf("%s: guessing MII\n", sc->sc_dev.dv_xname);
919 sc->xl_media = XL_MEDIAOPT_BT4;
920 sc->xl_xcvr = XL_XCVR_MII;
922 printf("%s: guessing 100BaseT4/MII\n", sc->sc_dev.dv_xname);
930 sc->xl_media = XL_MEDIAOPT_BTX;
931 sc->xl_xcvr = XL_XCVR_AUTO;
934 sc->sc_dev.dv_xname);
937 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
938 sc->xl_xcvr = XL_XCVR_AUTO;
941 sc->sc_dev.dv_xname);
945 "defaulting to 10baseT\n", sc->sc_dev.dv_xname, devid);
946 sc->xl_media = XL_MEDIAOPT_BT;
955 xl_list_tx_init(struct xl_softc *sc)
961 cd = &sc->xl_cdata;
962 ld = sc->xl_ldata;
981 xl_list_tx_init_90xB(struct xl_softc *sc)
987 cd = &sc->xl_cdata;
988 ld = sc->xl_ldata;
1000 sc->sc_listmap->dm_segs[0].ds_addr +
1022 xl_list_rx_init(struct xl_softc *sc)
1029 cd = &sc->xl_cdata;
1030 ld = sc->xl_ldata;
1040 next = sc->sc_listmap->dm_segs[0].ds_addr +
1047 xl_fill_rx_ring(sc);
1052 xl_fill_rx_ring(struct xl_softc *sc)
1057 cd = &sc->xl_cdata;
1061 if (xl_newbuf(sc, cd->xl_rx_prod) == ENOBUFS)
1072 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1082 if (bus_dmamap_load(sc->sc_dmat, sc->sc_rx_sparemap,
1090 bus_dmamap_sync(sc->sc_dmat, c->map,
1092 bus_dmamap_unload(sc->sc_dmat, c->map);
1096 c->map = sc->sc_rx_sparemap;
1097 sc->sc_rx_sparemap = map;
1102 bus_dmamap_sync(sc->sc_dmat, c->map, 0, c->map->dm_mapsize,
1112 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1113 ((caddr_t)c->xl_ptr - sc->sc_listkva), sizeof(struct xl_list),
1124 xl_rxeof(struct xl_softc *sc)
1134 ifp = &sc->sc_arpcom.ac_if;
1138 while (if_rxr_inuse(&sc->xl_cdata.xl_rx_ring) > 0) {
1139 cur_rx = sc->xl_cdata.xl_rx_cons;
1140 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1141 ((caddr_t)cur_rx->xl_ptr - sc->sc_listkva),
1144 if ((rxstat = letoh32(sc->xl_cdata.xl_rx_cons->xl_ptr->xl_status)) == 0)
1148 sc->xl_cdata.xl_rx_cons = cur_rx->xl_next;
1149 if_rxr_put(&sc->xl_cdata.xl_rx_ring, 1);
1181 "packet dropped\n", sc->sc_dev.dv_xname);
1190 if (sc->xl_type == XL_TYPE_905B) {
1210 if_rxr_livelocked(&sc->xl_cdata.xl_rx_ring);
1212 xl_fill_rx_ring(sc);
1226 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1227 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1228 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1229 xl_wait(sc);
1230 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1231 xl_fill_rx_ring(sc);
1241 xl_txeof(struct xl_softc *sc)
1246 ifp = &sc->sc_arpcom.ac_if;
1257 while (sc->xl_cdata.xl_tx_head != NULL) {
1258 cur_tx = sc->xl_cdata.xl_tx_head;
1260 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1261 ((caddr_t)cur_tx->xl_ptr - sc->sc_listkva),
1265 if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
1268 sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
1272 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1274 bus_dmamap_unload(sc->sc_dmat, map);
1280 cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
1281 sc->xl_cdata.xl_tx_free = cur_tx;
1284 if (sc->xl_cdata.xl_tx_head == NULL) {
1288 sc->xl_cdata.xl_tx_tail = NULL;
1290 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
1291 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
1292 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1293 sc->sc_listmap->dm_segs[0].ds_addr +
1294 ((caddr_t)sc->xl_cdata.xl_tx_head->xl_ptr -
1295 sc->sc_listkva));
1296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1302 xl_txeof_90xB(struct xl_softc *sc)
1308 ifp = &sc->sc_arpcom.ac_if;
1310 idx = sc->xl_cdata.xl_tx_cons;
1311 while (idx != sc->xl_cdata.xl_tx_prod) {
1313 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
1325 bus_dmamap_sync(sc->sc_dmat, cur_tx->map,
1327 bus_dmamap_unload(sc->sc_dmat, cur_tx->map);
1330 sc->xl_cdata.xl_tx_cnt--;
1334 sc->xl_cdata.xl_tx_cons = idx;
1338 if (sc->xl_cdata.xl_tx_cnt == 0)
1348 xl_txeoc(struct xl_softc *sc)
1352 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
1358 sc->sc_dev.dv_xname, txstat);
1360 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1361 xl_wait(sc);
1362 if (sc->xl_type == XL_TYPE_905B) {
1363 if (sc->xl_cdata.xl_tx_cnt) {
1367 i = sc->xl_cdata.xl_tx_cons;
1368 c = &sc->xl_cdata.xl_tx_chain[i];
1369 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1371 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
1374 if (sc->xl_cdata.xl_tx_head != NULL)
1375 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1376 sc->sc_listmap->dm_segs[0].ds_addr +
1377 ((caddr_t)sc->xl_cdata.xl_tx_head->xl_ptr -
1378 sc->sc_listkva));
1384 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
1386 sc->xl_tx_thresh < XL_PACKET_SIZE) {
1387 sc->xl_tx_thresh += XL_MIN_FRAMELEN;
1390 " threshold to %d\n", sc->sc_dev.dv_xname,
1391 sc->xl_tx_thresh);
1394 CSR_WRITE_2(sc, XL_COMMAND,
1395 XL_CMD_TX_SET_START|sc->xl_tx_thresh);
1396 if (sc->xl_type == XL_TYPE_905B) {
1397 CSR_WRITE_2(sc, XL_COMMAND,
1400 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
1401 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1403 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
1404 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1410 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
1417 struct xl_softc *sc;
1422 sc = arg;
1423 ifp = &sc->sc_arpcom.ac_if;
1425 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && status != 0xFFFF) {
1429 CSR_WRITE_2(sc, XL_COMMAND,
1432 if (sc->intr_ack)
1433 (*sc->intr_ack)(sc);
1439 xl_rxeof(sc);
1442 if (sc->xl_type == XL_TYPE_905B)
1443 xl_txeof_90xB(sc);
1445 xl_txeof(sc);
1450 xl_txeoc(sc);
1454 xl_init(sc);
1457 sc->xl_stats_no_timeout = 1;
1458 xl_stats_update(sc);
1459 sc->xl_stats_no_timeout = 0;
1472 struct xl_softc *sc;
1481 sc = xsc;
1482 ifp = &sc->sc_arpcom.ac_if;
1483 if (sc->xl_hasmii)
1484 mii = &sc->sc_mii;
1492 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
1507 CSR_READ_1(sc, XL_W4_BADSSD);
1509 if (mii != NULL && (!sc->xl_stats_no_timeout))
1514 if (!sc->xl_stats_no_timeout)
1515 timeout_add_sec(&sc->xl_stsup_tmo, 1);
1523 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf *m_head)
1529 map = sc->sc_tx_sparemap;
1532 error = bus_dmamap_load_mbuf(sc->sc_dmat, map,
1587 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1591 bus_dmamap_sync(sc->sc_dmat, c->map,
1593 bus_dmamap_unload(sc->sc_dmat, c->map);
1597 sc->sc_tx_sparemap = c->map;
1603 if (sc->xl_type == XL_TYPE_905B) {
1619 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1636 struct xl_softc *sc;
1642 sc = ifp->if_softc;
1648 if (sc->xl_cdata.xl_tx_free == NULL) {
1649 xl_txeoc(sc);
1650 xl_txeof(sc);
1651 if (sc->xl_cdata.xl_tx_free == NULL) {
1657 start_tx = sc->xl_cdata.xl_tx_free;
1659 while (sc->xl_cdata.xl_tx_free != NULL) {
1666 cur_tx = sc->xl_cdata.xl_tx_free;
1669 error = xl_encap(sc, cur_tx, m_head);
1675 sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
1682 sc->sc_listmap->dm_segs[0].ds_addr +
1683 ((caddr_t)cur_tx->xl_ptr - sc->sc_listkva);
1718 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
1719 xl_wait(sc);
1721 if (sc->xl_cdata.xl_tx_head != NULL) {
1722 sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
1723 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
1724 sc->sc_listmap->dm_segs[0].ds_addr +
1725 ((caddr_t)start_tx->xl_ptr - sc->sc_listkva);
1726 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
1728 sc->xl_cdata.xl_tx_tail = cur_tx;
1730 sc->xl_cdata.xl_tx_head = start_tx;
1731 sc->xl_cdata.xl_tx_tail = cur_tx;
1733 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
1734 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1735 sc->sc_listmap->dm_segs[0].ds_addr +
1736 ((caddr_t)start_tx->xl_ptr - sc->sc_listkva));
1738 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1762 xl_rxeof(sc);
1768 struct xl_softc *sc;
1774 sc = ifp->if_softc;
1779 idx = sc->xl_cdata.xl_tx_prod;
1780 start_tx = &sc->xl_cdata.xl_tx_chain[idx];
1782 while (sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL) {
1784 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
1794 cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
1797 error = xl_encap(sc, cur_tx, m_head);
1819 sc->xl_cdata.xl_tx_cnt++;
1838 sc->xl_cdata.xl_tx_prod = idx;
1850 struct xl_softc *sc = xsc;
1851 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1860 xl_stop(sc);
1863 xl_reset(sc);
1865 if (sc->xl_hasmii)
1866 mii = &sc->sc_mii;
1869 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1870 xl_wait(sc);
1872 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1873 xl_wait(sc);
1879 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
1880 sc->sc_arpcom.ac_enaddr[i]);
1885 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
1888 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
1889 xl_wait(sc);
1890 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
1891 xl_wait(sc);
1894 if (xl_list_rx_init(sc) == ENOBUFS) {
1896 "memory for rx buffers\n", sc->sc_dev.dv_xname);
1897 xl_stop(sc);
1903 if (sc->xl_type == XL_TYPE_905B)
1904 xl_list_tx_init_90xB(sc);
1906 xl_list_tx_init(sc);
1914 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
1917 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
1928 if (sc->xl_type == XL_TYPE_905B) {
1929 CSR_WRITE_2(sc, XL_COMMAND,
1934 xl_iff(sc);
1946 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1947 xl_wait(sc);
1948 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->sc_listmap->dm_segs[0].ds_addr +
1950 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1951 xl_wait(sc);
1953 if (sc->xl_type == XL_TYPE_905B) {
1955 CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
1957 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
1958 xl_wait(sc);
1959 CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
1960 sc->sc_listmap->dm_segs[0].ds_addr +
1962 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
1963 xl_wait(sc);
1971 if (sc->xl_xcvr == XL_XCVR_COAX)
1972 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
1974 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
1983 if (sc->xl_type == XL_TYPE_905B)
1984 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
1987 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
1989 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
1993 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
1994 sc->xl_stats_no_timeout = 1;
1995 xl_stats_update(sc);
1996 sc->xl_stats_no_timeout = 0;
1998 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
1999 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2004 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2005 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2006 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2008 if (sc->intr_ack)
2009 (*sc->intr_ack)(sc);
2012 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2013 CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2016 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2017 xl_wait(sc);
2018 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2019 xl_wait(sc);
2033 timeout_add_sec(&sc->xl_stsup_tmo, 1);
2042 struct xl_softc *sc;
2046 sc = ifp->if_softc;
2048 if (sc->xl_hasmii)
2049 mii = &sc->sc_mii;
2051 ifm = &sc->ifmedia;
2060 xl_setmode(sc, ifm->ifm_media);
2067 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2068 || sc->xl_media & XL_MEDIAOPT_BT4) {
2069 xl_init(sc);
2071 xl_setmode(sc, ifm->ifm_media);
2083 struct xl_softc *sc;
2088 sc = ifp->if_softc;
2089 if (sc->xl_hasmii != 0)
2090 mii = &sc->sc_mii;
2093 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2096 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2108 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2114 if (sc->xl_type == XL_TYPE_905B &&
2115 sc->xl_media == XL_MEDIAOPT_10FL) {
2117 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2144 printf("%s: unknown XCVR type: %d\n", sc->sc_dev.dv_xname, icfg);
2152 struct xl_softc *sc = ifp->if_softc;
2163 xl_init(sc);
2171 xl_init(sc);
2174 xl_stop(sc);
2180 if (sc->xl_hasmii != 0)
2181 mii = &sc->sc_mii;
2184 &sc->ifmedia, command);
2192 NULL, MCLBYTES, &sc->xl_cdata.xl_rx_ring);
2196 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data);
2201 xl_iff(sc);
2212 struct xl_softc *sc;
2215 sc = ifp->if_softc;
2219 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2220 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
2224 sc->sc_dev.dv_xname);
2225 xl_txeoc(sc);
2226 xl_txeof(sc);
2227 xl_rxeof(sc);
2228 xl_init(sc);
2235 xl_freetxrx(struct xl_softc *sc)
2244 if (sc->xl_cdata.xl_rx_chain[i].map->dm_nsegs != 0) {
2245 map = sc->xl_cdata.xl_rx_chain[i].map;
2247 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2249 bus_dmamap_unload(sc->sc_dmat, map);
2251 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
2252 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
2253 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
2256 bzero(&sc->xl_ldata->xl_rx_list, sizeof(sc->xl_ldata->xl_rx_list));
2261 if (sc->xl_cdata.xl_tx_chain[i].map->dm_nsegs != 0) {
2262 map = sc->xl_cdata.xl_tx_chain[i].map;
2264 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2266 bus_dmamap_unload(sc->sc_dmat, map);
2268 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
2269 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
2270 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
2273 bzero(&sc->xl_ldata->xl_tx_list, sizeof(sc->xl_ldata->xl_tx_list));
2281 xl_stop(struct xl_softc *sc)
2286 timeout_del(&sc->xl_stsup_tmo);
2288 ifp = &sc->sc_arpcom.ac_if;
2294 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
2295 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2296 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
2297 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
2298 xl_wait(sc);
2299 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
2300 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2304 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2305 xl_wait(sc);
2306 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2307 xl_wait(sc);
2310 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
2311 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
2312 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2314 if (sc->intr_ack)
2315 (*sc->intr_ack)(sc);
2317 xl_freetxrx(sc);
2322 xl_wol_power(struct xl_softc *sc)
2326 if ((sc->xl_flags & XL_FLAG_WOL) && sc->wol_power) {
2327 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2328 sc->wol_power(sc->wol_power_arg);
2334 xl_attach(struct xl_softc *sc)
2338 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2344 xl_reset(sc);
2350 if (xl_read_eeprom(sc, (caddr_t)&enaddr, XL_EE_OEM_ADR0, 3, 1)) {
2352 sc->sc_dev.dv_xname);
2355 memcpy(&sc->sc_arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
2357 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct xl_list_data),
2358 PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg,
2363 if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg,
2364 sizeof(struct xl_list_data), &sc->sc_listkva,
2369 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct xl_list_data), 1,
2371 &sc->sc_listmap) != 0) {
2375 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva,
2380 sc->xl_ldata = (struct xl_list_data *)sc->sc_listkva;
2383 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
2385 &sc->xl_cdata.xl_rx_chain[i].map) != 0) {
2390 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
2391 BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) {
2397 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
2399 &sc->xl_cdata.xl_tx_chain[i].map) != 0) {
2404 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, XL_TX_LIST_CNT - 3,
2405 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) {
2410 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
2412 if (sc->xl_flags & (XL_FLAG_INVERT_LED_PWR|XL_FLAG_INVERT_MII_PWR)) {
2416 n = CSR_READ_2(sc, 12);
2418 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR)
2421 if (sc->xl_flags & XL_FLAG_INVERT_MII_PWR)
2424 CSR_WRITE_2(sc, 12, n);
2437 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
2438 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
2439 !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
2440 sc->xl_type = XL_TYPE_905B;
2442 sc->xl_type = XL_TYPE_90X;
2445 sc->xl_tx_thresh = XL_MIN_FRAMELEN;
2447 timeout_set(&sc->xl_stsup_tmo, xl_stats_update, sc);
2449 ifp->if_softc = sc;
2452 if (sc->xl_type == XL_TYPE_905B)
2459 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
2469 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
2471 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
2472 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
2473 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
2474 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
2476 xl_mediacheck(sc);
2478 if (sc->xl_media & XL_MEDIAOPT_MII || sc->xl_media & XL_MEDIAOPT_BTX
2479 || sc->xl_media & XL_MEDIAOPT_BT4) {
2480 ifmedia_init(&sc->sc_mii.mii_media, 0,
2482 sc->xl_hasmii = 1;
2483 sc->sc_mii.mii_ifp = ifp;
2484 sc->sc_mii.mii_readreg = xl_miibus_readreg;
2485 sc->sc_mii.mii_writereg = xl_miibus_writereg;
2486 sc->sc_mii.mii_statchg = xl_miibus_statchg;
2487 xl_setcfg(sc);
2488 mii_attach((struct device *)sc, &sc->sc_mii, 0xffffffff,
2491 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
2492 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,
2494 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
2497 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
2499 ifm = &sc->sc_mii.mii_media;
2502 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
2503 sc->xl_hasmii = 0;
2504 ifm = &sc->ifmedia;
2512 if (sc->xl_xcvr == XL_XCVR_AUTO)
2513 xl_choose_xcvr(sc, 0);
2515 if (sc->xl_media & XL_MEDIAOPT_BT) {
2518 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
2522 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
2526 if (sc->xl_type == XL_TYPE_905B &&
2527 sc->xl_media == XL_MEDIAOPT_10FL) {
2531 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
2539 if (sc->xl_media & XL_MEDIAOPT_BNC) {
2543 if (sc->xl_media & XL_MEDIAOPT_BFX) {
2549 switch(sc->xl_xcvr) {
2552 xl_setmode(sc, media);
2555 if (sc->xl_type == XL_TYPE_905B &&
2556 sc->xl_media == XL_MEDIAOPT_10FL) {
2558 xl_setmode(sc, media);
2561 xl_setmode(sc, media);
2566 xl_setmode(sc, media);
2575 xl_setmode(sc, media);
2578 printf("%s: unknown XCVR type: %d\n", sc->sc_dev.dv_xname,
2579 sc->xl_xcvr);
2588 if (sc->xl_hasmii == 0)
2589 ifmedia_set(&sc->ifmedia, media);
2591 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
2593 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
2598 if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0) {
2613 xl_detach(struct xl_softc *sc)
2615 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2619 timeout_del(&sc->xl_stsup_tmo);
2621 xl_freetxrx(sc);
2624 if (sc->xl_hasmii)
2625 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
2628 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY);
2640 struct xl_softc *sc = ifp->if_softc;
2645 xl_init(sc);
2646 CSR_WRITE_2(sc, XL_W7_BM_PME, XL_BM_PME_MAGIC);
2647 sc->xl_flags |= XL_FLAG_WOL;
2649 CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2650 sc->xl_flags &= ~XL_FLAG_WOL;