Lines Matching defs:sc
164 ti_eeprom_putbyte(struct ti_softc *sc, int byte)
171 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
178 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
180 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
182 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
184 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
190 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
195 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
196 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
197 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
208 ti_eeprom_getbyte(struct ti_softc *sc, int addr, u_int8_t *dest)
218 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
220 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
227 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
229 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
235 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
237 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
246 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
248 sc->sc_dv.dv_xname, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
255 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
257 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
259 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
261 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
280 ti_read_eeprom(struct ti_softc *sc, caddr_t dest, int off, int cnt)
286 err = ti_eeprom_getbyte(sc, off + i, &byte);
300 ti_mem_read(struct ti_softc *sc, u_int32_t addr, u_int32_t len, void *buf)
314 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
315 bus_space_read_region_4(sc->ti_btag, sc->ti_bhandle,
329 ti_mem_write(struct ti_softc *sc, u_int32_t addr, u_int32_t len,
344 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
345 bus_space_write_region_4(sc->ti_btag, sc->ti_bhandle,
359 ti_mem_set(struct ti_softc *sc, u_int32_t addr, u_int32_t len)
371 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
372 bus_space_set_region_4(sc->ti_btag, sc->ti_bhandle,
385 ti_loadfw(struct ti_softc *sc)
394 switch(sc->ti_hwrev) {
403 sc->sc_dv.dv_xname);
421 "%d.%d.%d, got %d.%d.%d\n", sc->sc_dv.dv_xname,
428 ti_mem_write(sc, tf->FwTextAddr, tf->FwTextLen,
430 ti_mem_write(sc, tf->FwRodataAddr, tf->FwRodataLen,
432 ti_mem_write(sc, tf->FwDataAddr, tf->FwDataLen,
434 ti_mem_set(sc, tf->FwBssAddr, tf->FwBssLen);
435 ti_mem_set(sc, tf->FwSbssAddr, tf->FwSbssLen);
436 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tf->FwStartAddr);
444 ti_cmd(struct ti_softc *sc, struct ti_cmd_desc *cmd)
448 index = sc->ti_cmd_saved_prodidx;
449 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
451 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
452 sc->ti_cmd_saved_prodidx = index;
460 ti_cmd_ext(struct ti_softc *sc, struct ti_cmd_desc *cmd, caddr_t arg,
466 index = sc->ti_cmd_saved_prodidx;
467 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
470 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
474 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
475 sc->ti_cmd_saved_prodidx = index;
482 ti_handle_events(struct ti_softc *sc)
485 struct ifnet *ifp = &sc->arpcom.ac_if;
487 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
488 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
491 sc->ti_linkstat = TI_EVENT_CODE(e);
492 switch (sc->ti_linkstat) {
519 sc->sc_dv.dv_xname, sc->ti_linkstat);
525 sc->sc_dv.dv_xname);
528 sc->sc_dv.dv_xname);
531 sc->sc_dv.dv_xname);
534 ti_init2(sc);
537 ti_stats_update(sc);
544 printf("%s: unknown event: %d\n", sc->sc_dv.dv_xname,
549 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
550 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
558 ti_newbuf_std(struct ti_softc *sc, int i, struct mbuf *m,
567 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES,
570 sc->sc_dv.dv_xname);
574 bus_dmamap_unload(sc->sc_dmatag, dmamap);
576 sc->ti_cdata.ti_rx_std_map[i] = dmamap;
586 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new,
603 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
604 r = &sc->ti_rdata->ti_rx_std_ring[i];
619 ti_newbuf_mini(struct ti_softc *sc, int i, struct mbuf *m,
628 if (bus_dmamap_create(sc->sc_dmatag, MHLEN, 1, MHLEN,
631 sc->sc_dv.dv_xname);
635 bus_dmamap_unload(sc->sc_dmatag, dmamap);
637 sc->ti_cdata.ti_rx_mini_map[i] = dmamap;
647 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new,
663 r = &sc->ti_rdata->ti_rx_mini_ring[i];
664 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
679 ti_newbuf_jumbo(struct ti_softc *sc, int i, struct mbuf *m,
688 if (bus_dmamap_create(sc->sc_dmatag, TI_JUMBO_FRAMELEN, 1,
691 sc->sc_dv.dv_xname);
695 bus_dmamap_unload(sc->sc_dmatag, dmamap);
705 if (bus_dmamap_load_mbuf(sc->sc_dmatag, dmamap, m_new,
723 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
724 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
741 ti_init_rx_ring_std(struct ti_softc *sc)
747 if (ti_newbuf_std(sc, i, NULL, 0) == ENOBUFS)
751 TI_UPDATE_STDPROD(sc, i - 1);
752 sc->ti_std = i - 1;
758 ti_free_rx_ring_std(struct ti_softc *sc)
763 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
764 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
765 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
766 bus_dmamap_destroy(sc->sc_dmatag,
767 sc->ti_cdata.ti_rx_std_map[i]);
768 sc->ti_cdata.ti_rx_std_map[i] = 0;
770 bzero(&sc->ti_rdata->ti_rx_std_ring[i],
776 ti_init_rx_ring_jumbo(struct ti_softc *sc)
782 if (ti_newbuf_jumbo(sc, i, NULL, 0) == ENOBUFS)
786 TI_UPDATE_JUMBOPROD(sc, i - 1);
787 sc->ti_jumbo = i - 1;
793 ti_free_rx_ring_jumbo(struct ti_softc *sc)
798 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
799 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
800 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
802 bzero(&sc->ti_rdata->ti_rx_jumbo_ring[i],
808 ti_init_rx_ring_mini(struct ti_softc *sc)
813 if (ti_newbuf_mini(sc, i, NULL, 0) == ENOBUFS)
817 TI_UPDATE_MINIPROD(sc, i - 1);
818 sc->ti_mini = i - 1;
824 ti_free_rx_ring_mini(struct ti_softc *sc)
829 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
830 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
831 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
832 bus_dmamap_destroy(sc->sc_dmatag,
833 sc->ti_cdata.ti_rx_mini_map[i]);
834 sc->ti_cdata.ti_rx_mini_map[i] = 0;
836 bzero(&sc->ti_rdata->ti_rx_mini_ring[i],
842 ti_free_tx_ring(struct ti_softc *sc)
848 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
849 m_freem(sc->ti_cdata.ti_tx_chain[i]);
850 sc->ti_cdata.ti_tx_chain[i] = NULL;
851 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead,
852 sc->ti_cdata.ti_tx_map[i], link);
853 sc->ti_cdata.ti_tx_map[i] = 0;
855 bzero(&sc->ti_rdata->ti_tx_ring[i],
859 while ((entry = SLIST_FIRST(&sc->ti_tx_map_listhead))) {
860 SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link);
861 bus_dmamap_destroy(sc->sc_dmatag, entry->dmamap);
867 ti_init_tx_ring(struct ti_softc *sc)
873 sc->ti_txcnt = 0;
874 sc->ti_tx_saved_considx = 0;
875 sc->ti_tx_saved_prodidx = 0;
876 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
878 SLIST_INIT(&sc->ti_tx_map_listhead);
880 if (bus_dmamap_create(sc->sc_dmatag, TI_JUMBO_FRAMELEN,
886 bus_dmamap_destroy(sc->sc_dmatag, dmamap);
890 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry, link);
902 ti_add_mcast(struct ti_softc *sc, struct ether_addr *addr)
910 switch(sc->ti_hwrev) {
912 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
913 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
922 printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname);
928 ti_del_mcast(struct ti_softc *sc, struct ether_addr *addr)
936 switch(sc->ti_hwrev) {
938 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
939 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
948 printf("%s: unknown hwrev\n", sc->sc_dv.dv_xname);
968 ti_iff(struct ti_softc *sc)
970 struct ifnet *ifp = &sc->arpcom.ac_if;
971 struct arpcom *ac = &sc->arpcom;
993 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
994 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
997 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
998 mc = SLIST_FIRST(&sc->ti_mc_listhead);
999 ti_del_mcast(sc, &mc->mc_addr);
1000 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1014 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc,
1016 ti_add_mcast(sc, &mc->mc_addr);
1022 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1033 ti_64bitslot_war(struct ti_softc *sc)
1035 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1036 CSR_WRITE_4(sc, 0x600, 0);
1037 CSR_WRITE_4(sc, 0x604, 0);
1038 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1039 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1040 if (sc->ti_hwrev == TI_HWREV_TIGON)
1043 TI_SETBIT(sc, TI_PCI_STATE,
1058 ti_chipinit(struct ti_softc *sc)
1063 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1066 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1070 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1072 sc->sc_dv.dv_xname);
1077 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1080 chip_rev = CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK;
1083 sc->ti_hwrev = TI_HWREV_TIGON;
1086 sc->ti_hwrev = TI_HWREV_TIGON_II;
1091 sc->sc_dv.dv_xname, chip_rev);
1096 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1097 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1098 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1099 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1102 if (sc->ti_sbus)
1103 ti_chipinit_sbus(sc);
1105 ti_chipinit_pci(sc);
1108 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1109 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1111 if (ti_64bitslot_war(sc)) {
1113 "but we aren't", sc->sc_dv.dv_xname);
1121 ti_chipinit_pci(struct ti_softc *sc)
1127 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD);
1128 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
1129 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1132 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1136 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1144 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCI_COMMAND_INVALIDATE_ENABLE) {
1155 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1169 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1171 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1175 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1178 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_DMA_SWAP_OPTIONS |
1184 ti_chipinit_sbus(struct ti_softc *sc)
1187 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD | TI_PCI_WRITE_CMD |
1193 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_WORDSWAP_BD |
1204 ti_gibinit(struct ti_softc *sc)
1210 ifp = &sc->arpcom.ac_if;
1213 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1221 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1222 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO,
1223 TI_RING_DMA_ADDR(sc, ti_info) & 0xffffffff);
1226 ti_loadfw(sc);
1231 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1233 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_event_ring);
1235 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1236 TI_RING_DMA_ADDR(sc, ti_ev_prodidx_r);
1237 sc->ti_ev_prodidx.ti_idx = 0;
1238 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1239 sc->ti_ev_saved_considx = 0;
1242 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1248 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1250 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1251 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1252 sc->ti_cmd_saved_prodidx = 0;
1259 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1260 TI_RING_DMA_ADDR(sc, ti_info.ti_stats);
1263 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1265 TI_RING_DMA_ADDR(sc, ti_rx_std_ring);
1275 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1276 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_rx_jumbo_ring);
1290 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1291 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc, ti_rx_mini_ring);
1293 if (sc->ti_hwrev == TI_HWREV_TIGON)
1306 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1307 TI_HOSTADDR(rcb->ti_hostaddr) = TI_RING_DMA_ADDR(sc,ti_rx_return_ring);
1310 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1311 TI_RING_DMA_ADDR(sc, ti_return_prodidx_r);
1322 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1323 bzero(sc->ti_rdata->ti_tx_ring,
1325 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1326 if (sc->ti_hwrev == TI_HWREV_TIGON)
1336 if (sc->ti_hwrev == TI_HWREV_TIGON)
1340 TI_RING_DMA_ADDR(sc, ti_tx_ring);
1341 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1342 TI_RING_DMA_ADDR(sc, ti_tx_considx_r);
1344 TI_RING_DMASYNC(sc, ti_info, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1347 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, (sc->ti_rx_coal_ticks / 10));
1348 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1349 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1350 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1351 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1352 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1355 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1356 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1359 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1365 ti_attach(struct ti_softc *sc)
1372 if (ti_chipinit(sc)) {
1373 printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname);
1378 ti_mem_set(sc, 0x2000, 0x100000 - 0x2000);
1381 if (ti_chipinit(sc)) {
1382 printf("%s: chip initialization failed\n", sc->sc_dv.dv_xname);
1393 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1396 sc->sc_dv.dv_xname);
1403 printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
1406 if (bus_dmamem_alloc(sc->sc_dmatag, sizeof(struct ti_ring_data),
1408 printf("%s: can't alloc rx buffers\n", sc->sc_dv.dv_xname);
1411 if (bus_dmamem_map(sc->sc_dmatag, &seg, rseg,
1414 sc->sc_dv.dv_xname, sizeof(struct ti_ring_data));
1417 if (bus_dmamap_create(sc->sc_dmatag, sizeof(struct ti_ring_data), 1,
1419 &sc->ti_ring_map)) {
1420 printf("%s: can't create dma map\n", sc->sc_dv.dv_xname);
1423 if (bus_dmamap_load(sc->sc_dmatag, sc->ti_ring_map, kva,
1427 sc->ti_rdata = (struct ti_ring_data *)kva;
1428 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1431 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1432 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1433 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1434 sc->ti_rx_max_coal_bds = 64;
1435 sc->ti_tx_max_coal_bds = 128;
1436 sc->ti_tx_buf_ratio = 21;
1439 ifp = &sc->arpcom.ac_if;
1440 ifp->if_softc = sc;
1447 bcopy(sc->sc_dv.dv_xname, ifp->if_xname, IFNAMSIZ);
1456 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1457 if (sc->ti_copper) {
1466 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1467 ifmedia_add(&sc->ifmedia,
1469 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1470 ifmedia_add(&sc->ifmedia,
1472 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
1473 ifmedia_add(&sc->ifmedia,
1477 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1478 ifmedia_add(&sc->ifmedia,
1481 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1482 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1493 bus_dmamap_destroy(sc->sc_dmatag, sc->ti_ring_map);
1496 bus_dmamem_unmap(sc->sc_dmatag, kva,
1500 bus_dmamem_free(sc->sc_dmatag, &seg, rseg);
1517 ti_rxeof(struct ti_softc *sc)
1523 ifp = &sc->arpcom.ac_if;
1525 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1532 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1534 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1537 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1538 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1539 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1540 dmamap = sc->ti_cdata.ti_rx_jumbo_map[rxidx];
1541 sc->ti_cdata.ti_rx_jumbo_map[rxidx] = 0;
1544 ti_newbuf_jumbo(sc, sc->ti_jumbo, m, dmamap);
1547 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL, dmamap)
1550 ti_newbuf_jumbo(sc, sc->ti_jumbo, m, dmamap);
1554 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1555 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1556 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1557 dmamap = sc->ti_cdata.ti_rx_mini_map[rxidx];
1558 sc->ti_cdata.ti_rx_mini_map[rxidx] = 0;
1561 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
1564 if (ti_newbuf_mini(sc, sc->ti_mini, NULL, dmamap)
1567 ti_newbuf_mini(sc, sc->ti_mini, m, dmamap);
1571 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1572 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1573 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1574 dmamap = sc->ti_cdata.ti_rx_std_map[rxidx];
1575 sc->ti_cdata.ti_rx_std_map[rxidx] = 0;
1578 ti_newbuf_std(sc, sc->ti_std, m, dmamap);
1581 if (ti_newbuf_std(sc, sc->ti_std, NULL, dmamap)
1584 ti_newbuf_std(sc, sc->ti_std, m, dmamap);
1590 panic("%s: couldn't get mbuf", sc->sc_dv.dv_xname);
1608 if (sc->ti_hwrev == TI_HWREV_TIGON)
1609 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1610 sc->ti_rx_saved_considx);
1612 TI_UPDATE_STDPROD(sc, sc->ti_std);
1613 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1614 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1620 ti_txeof_tigon1(struct ti_softc *sc)
1626 ifp = &sc->arpcom.ac_if;
1632 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1636 idx = sc->ti_tx_saved_considx;
1637 ti_mem_read(sc, TI_TX_RING_BASE + idx * sizeof(txdesc),
1640 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1641 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1642 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1644 entry = sc->ti_cdata.ti_tx_map[idx];
1645 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
1648 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
1649 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry,
1651 sc->ti_cdata.ti_tx_map[idx] = NULL;
1654 sc->ti_txcnt--;
1655 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1666 ti_txeof_tigon2(struct ti_softc *sc)
1672 ifp = &sc->arpcom.ac_if;
1678 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1681 idx = sc->ti_tx_saved_considx;
1682 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1684 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1685 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1686 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1688 entry = sc->ti_cdata.ti_tx_map[idx];
1689 bus_dmamap_sync(sc->sc_dmatag, entry->dmamap, 0,
1692 bus_dmamap_unload(sc->sc_dmatag, entry->dmamap);
1693 SLIST_INSERT_HEAD(&sc->ti_tx_map_listhead, entry,
1695 sc->ti_cdata.ti_tx_map[idx] = NULL;
1698 sc->ti_txcnt--;
1699 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1710 struct ti_softc *sc;
1713 sc = xsc;
1714 ifp = &sc->arpcom.ac_if;
1718 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE))
1722 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1726 ti_rxeof(sc);
1729 if (sc->ti_hwrev == TI_HWREV_TIGON)
1730 ti_txeof_tigon1(sc);
1732 ti_txeof_tigon2(sc);
1735 ti_handle_events(sc);
1738 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1747 ti_stats_update(struct ti_softc *sc)
1750 struct ti_stats *stats = &sc->ti_rdata->ti_info.ti_stats;
1752 ifp = &sc->arpcom.ac_if;
1754 TI_RING_DMASYNC(sc, ti_info.ti_stats, BUS_DMASYNC_POSTREAD);
1762 TI_RING_DMASYNC(sc, ti_info.ti_stats, BUS_DMASYNC_PREREAD);
1770 ti_encap_tigon1(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
1778 entry = SLIST_FIRST(&sc->ti_tx_map_listhead);
1790 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1798 if (txmap->dm_nsegs > (TI_TX_RING_CNT - sc->ti_txcnt - 16))
1802 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1819 ti_mem_write(sc, TI_TX_RING_BASE + frag * sizeof(txdesc),
1826 if (frag == sc->ti_tx_saved_considx)
1830 ti_mem_write(sc, TI_TX_RING_BASE + cur * sizeof(txdesc),
1833 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1836 sc->ti_cdata.ti_tx_chain[cur] = m_head;
1837 SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link);
1838 sc->ti_cdata.ti_tx_map[cur] = entry;
1839 sc->ti_txcnt += txmap->dm_nsegs;
1846 bus_dmamap_unload(sc->sc_dmatag, txmap);
1856 ti_encap_tigon2(struct ti_softc *sc, struct mbuf *m_head, u_int32_t *txidx)
1864 entry = SLIST_FIRST(&sc->ti_tx_map_listhead);
1876 if (bus_dmamap_load_mbuf(sc->sc_dmatag, txmap, m_head,
1884 if (txmap->dm_nsegs > (TI_TX_RING_CNT - sc->ti_txcnt - 16))
1888 f = &sc->ti_rdata->ti_tx_ring[frag];
1890 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1909 if (frag == sc->ti_tx_saved_considx)
1912 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
1914 bus_dmamap_sync(sc->sc_dmatag, txmap, 0, txmap->dm_mapsize,
1917 TI_RING_DMASYNC(sc, ti_tx_ring[cur], BUS_DMASYNC_POSTREAD);
1919 sc->ti_cdata.ti_tx_chain[cur] = m_head;
1920 SLIST_REMOVE_HEAD(&sc->ti_tx_map_listhead, link);
1921 sc->ti_cdata.ti_tx_map[cur] = entry;
1922 sc->ti_txcnt += txmap->dm_nsegs;
1929 bus_dmamap_unload(sc->sc_dmatag, txmap);
1941 struct ti_softc *sc;
1946 sc = ifp->if_softc;
1948 prodidx = sc->ti_tx_saved_prodidx;
1950 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
1960 if (sc->ti_hwrev == TI_HWREV_TIGON)
1961 error = ti_encap_tigon1(sc, m_head, &prodidx);
1963 error = ti_encap_tigon2(sc, m_head, &prodidx);
1988 sc->ti_tx_saved_prodidx = prodidx;
1989 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2000 struct ti_softc *sc = xsc;
2006 ti_stop(sc);
2009 if (ti_gibinit(sc)) {
2010 printf("%s: initialization failure\n", sc->sc_dv.dv_xname);
2019 ti_init2(struct ti_softc *sc)
2027 ifp = &sc->arpcom.ac_if;
2030 CSR_WRITE_4(sc, TI_GCR_IFINDEX, sc->sc_dv.dv_unit);
2031 CSR_WRITE_4(sc, TI_GCR_IFMTU,
2036 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2037 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2038 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2042 ti_iff(sc);
2048 if (sc->ti_hwrev == TI_HWREV_TIGON)
2052 if (ti_init_rx_ring_std(sc) == ENOBUFS)
2056 ti_init_rx_ring_jumbo(sc);
2062 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2063 ti_init_rx_ring_mini(sc);
2065 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2066 sc->ti_rx_saved_considx = 0;
2069 ti_init_tx_ring(sc);
2075 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2086 ifm = &sc->ifmedia;
2099 struct ti_softc *sc;
2103 sc = ifp->if_softc;
2104 ifm = &sc->ifmedia;
2111 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2114 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2122 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2124 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2126 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2135 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2136 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2139 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2141 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2144 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2146 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2162 struct ti_softc *sc;
2165 sc = ifp->if_softc;
2170 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN) {
2177 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2178 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2179 if (sc->ti_copper)
2187 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2188 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2189 if (sc->ti_copper) {
2210 struct ti_softc *sc = ifp->if_softc;
2220 ti_init(sc);
2228 ti_init(sc);
2231 ti_stop(sc);
2237 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2241 error = ether_ioctl(ifp, &sc->arpcom, command, data);
2246 ti_iff(sc);
2257 struct ti_softc *sc;
2259 sc = ifp->if_softc;
2261 printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname);
2262 ti_stop(sc);
2263 ti_init(sc);
2273 ti_stop(struct ti_softc *sc)
2278 ifp = &sc->arpcom.ac_if;
2284 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2291 ti_chipinit(sc);
2292 ti_mem_set(sc, 0x2000, 0x100000 - 0x2000);
2293 ti_chipinit(sc);
2296 ti_free_rx_ring_std(sc);
2299 ti_free_rx_ring_jumbo(sc);
2302 ti_free_rx_ring_mini(sc);
2305 ti_free_tx_ring(sc);
2307 sc->ti_ev_prodidx.ti_idx = 0;
2308 sc->ti_return_prodidx.ti_idx = 0;
2309 sc->ti_tx_considx.ti_idx = 0;
2310 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;