Lines Matching full:only
56 #define SCNTL2_CHM 0x40 /* 875 only */
57 #define SCNTL2_SLPMD 0x20 /* 875 only */
58 #define SCNTL2_SLPHBEN 0x10 /* 875 only */
59 #define SCNTL2_WSS 0x08 /* 875 only */
60 #define SCNTL2_VUE0 0x04 /* 875 only */
61 #define SCNTL2_VUE1 0x02 /* 875 only */
62 #define SCNTL2_WSR 0x01 /* 875 only */
65 #define SCNTL3_ULTRA 0x80 /* 875 only */
68 #define SCNTL3_EWS 0x08 /* 875 only */
122 #define GPREG_GPIO4 0x10 /* 875 only */
123 #define GPREG_GPIO3 0x08 /* 875 only */
124 #define GPREG_GPIO2 0x04 /* 875 only */
174 #define SSTAT2_ILF1 0x80 /* 875 only */
175 #define SSTAT2_ORF1 0x40 /* 875 only */
176 #define SSTAT2_OLF1 0x20 /* 875 only */
177 #define SSTAT2_FF4 0x10 /* 875 only */
178 #define SSTAT2_SPL1 0x08 /* 875 only */
179 #define SSTAT2_DF 0x04 /* 875 only */
181 #define SSTAT2_SDP1 0x01 /* 875 only */
201 #define CTEST2_SRTCH 0x04 /* 875 only */
287 #define SIEN1_SBMC 0x10 /* 895 only */
303 #define SIST1_SBMC 0x10 /* 895 only */
310 #define SIOP_SWIDE 0x45 /* scsi wide residue, RW, 875 only */
315 #define GPCNTL_ME 0x80 /* 875 only */
316 #define GPCNTL_FE 0x40 /* 875 only */
317 #define GPCNTL_IN4 0x10 /* 875 only */
318 #define GPCNTL_IN3 0x08 /* 875 only */
319 #define GPCNTL_IN2 0x04 /* 875 only */
330 #define STIME1_HTHBA 0x40 /* 875 only */
331 #define STIME1_GENSF 0x20 /* 875 only */
332 #define STIME1_HTHSF 0x10 /* 875 only */
338 #define SIOP_RESPID1 0x4B /* response ID, R/W, 875-only */
343 #define STEST1_DOGE 0x20 /* 1010 only */
344 #define STEST1_DIGE 0x10 /* 1010 only */
345 #define STEST1_DBLEN 0x08 /* 875-only */
346 #define STEST1_DBLSEL 0x04 /* 875-only */
349 #define STEST2_DIF 0x20 /* 875 only */
356 #define SIOP_STEST4 0x52 /* SCSI test 4, 895 only */
372 #define SIOP_SCRATCHC 0x60 /* Scratch register C, R/W, 875 only */
374 #define SIOP_SCRATCHD 0x64 /* Scratch register D, R/W, 875-only */
376 #define SIOP_SCRATCHE 0x68 /* Scratch register E, R/W, 875-only */
378 #define SIOP_SCRATCHF 0x6c /* Scratch register F, R/W, 875-only */
380 #define SIOP_SCRATCHG 0x70 /* Scratch register G, R/W, 875-only */
382 #define SIOP_SCRATCHH 0x74 /* Scratch register H, R/W, 875-only */
384 #define SIOP_SCRATCHI 0x78 /* Scratch register I, R/W, 875-only */
386 #define SIOP_SCRATCHJ 0x7c /* Scratch register J, R/W, 875-only */
388 #define SIOP_SCNTL4 0xBC /* SCSI control 4, R/W, 1010-only */
398 #define SIOP_AIPCNTL0 0xbe /* AIP Control 0, 1010-only */
403 #define SIOP_AIPCNTL1 0xbf /* AIP Control 1, 1010-only */
404 #define AIPCNTL1_DIS 0x08 /* disable AIP generation, 1010-66 only */
405 #define AIPCNTL1_RSETERR 0x04 /* reset AIP error 1010-66 only */
406 #define AIPCNTL1_FB 0x02 /* force bad AIP value 1010-66 only */
407 #define AIPCNTL1_RSET 0x01 /* reset AIP sequence value 1010-66 only */