Lines Matching defs:rtwn_bb_read
193 #define rtwn_bb_read rtwn_read_4
468 reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
470 reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
487 if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
488 val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
490 val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1118 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1123 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1144 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1149 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1899 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
1903 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
1908 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
1913 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
1917 reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
1951 reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2091 reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2094 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2100 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2105 reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2442 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
2444 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
2447 reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);
2451 reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);
2457 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
2461 reg = rtwn_bb_read(sc, 0x818);
2483 rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
2485 rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
2490 rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
2494 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
2497 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
2502 reg = rtwn_bb_read(sc, R92C_OFDM0_TX_PSDO_NOISE_WEIGHT);
2508 reg = rtwn_bb_read(sc,
2515 rtwn_bb_read(sc, R92C_OFDM0_RXAFE) |
2519 rtwn_bb_read(sc, R88F_RX_DFIR) &
2521 reg = rtwn_bb_read(sc, R88F_RX_DFIR);
2621 status = rtwn_bb_read(sc, 0xeac);
2626 tx[0] = (rtwn_bb_read(sc, R92C_TX_POWER_BEFORE_IQK_A + offset) >> 16)
2628 tx[1] = (rtwn_bb_read(sc, R92C_TX_POWER_AFTER_IQK_A + offset) >> 16)
2636 rx[0] = (rtwn_bb_read(sc, R92C_RX_POWER_BEFORE_IQK_A_2 + offset) >> 16)
2638 rx[1] = (rtwn_bb_read(sc, R92C_RX_POWER_AFTER_IQK_A_2 + offset) >> 16)
2668 xa_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0)) & 0xff;
2669 xb_agc = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1)) & 0xff;
2678 iq_cal_regs->adda[i] = rtwn_bb_read(sc, reg_adda[i]);
2697 rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2699 rtwn_bb_read(sc, R92C_OFDM0_TRMUXPAR);
2701 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
2703 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
2705 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
2707 rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
2709 rtwn_bb_read(sc, R92C_CONFIG_ANT_A);
2711 rtwn_bb_read(sc, R92C_CONFIG_ANT_B);
2713 rtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2720 hssi_param1 = rtwn_bb_read(sc, R92C_HSSI_PARAM1(0));
2735 rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0)) | (1 << 10) |
2738 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), rtwn_bb_read(sc,
2740 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), rtwn_bb_read(sc,
2858 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
2863 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
2912 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
2921 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);
2932 reg = rtwn_bb_read(sc, R92C_OFDM0_TXAFE(chain));
2937 reg = rtwn_bb_read(sc, R92C_OFDM0_TXIQIMBALANCE(chain));
2942 reg = rtwn_bb_read(sc, R92C_OFDM0_ECCATHRESHOLD);
2952 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQIMBALANCE(chain));
2962 reg = rtwn_bb_read(sc, R92C_OFDM0_RXIQEXTANTA);
2967 reg = rtwn_bb_read(sc, R92C_OFDM0_AGCRSSITABLE);
3290 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);
3293 reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);