Lines Matching defs:sc
195 #define DC_SETBIT(sc, reg, x) \
196 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
198 #define DC_CLRBIT(sc, reg, x) \
199 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
201 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x))
202 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x))
205 dc_delay(struct dc_softc *sc)
210 CSR_READ_4(sc, DC_BUSCTL);
214 dc_eeprom_width(struct dc_softc *sc)
219 dc_eeprom_idle(sc);
222 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
223 dc_delay(sc);
224 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
225 dc_delay(sc);
226 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
227 dc_delay(sc);
228 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
229 dc_delay(sc);
233 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
235 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
236 dc_delay(sc);
237 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
238 dc_delay(sc);
239 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
240 dc_delay(sc);
244 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
245 dc_delay(sc);
246 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) {
247 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
248 dc_delay(sc);
251 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
252 dc_delay(sc);
256 dc_eeprom_idle(sc);
259 sc->dc_romwidth = 6;
261 sc->dc_romwidth = i;
264 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
265 dc_delay(sc);
266 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
267 dc_delay(sc);
268 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
269 dc_delay(sc);
270 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
271 dc_delay(sc);
274 dc_eeprom_idle(sc);
278 dc_eeprom_idle(struct dc_softc *sc)
282 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
283 dc_delay(sc);
284 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
285 dc_delay(sc);
286 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
287 dc_delay(sc);
288 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
289 dc_delay(sc);
292 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
293 dc_delay(sc);
294 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
295 dc_delay(sc);
298 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
299 dc_delay(sc);
300 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS);
301 dc_delay(sc);
302 CSR_WRITE_4(sc, DC_SIO, 0x00000000);
309 dc_eeprom_putbyte(struct dc_softc *sc, int addr)
317 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
319 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN);
320 dc_delay(sc);
321 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK);
322 dc_delay(sc);
323 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
324 dc_delay(sc);
330 for (i = sc->dc_romwidth; i--;) {
336 dc_delay(sc);
338 dc_delay(sc);
340 dc_delay(sc);
350 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest)
355 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr);
359 r = CSR_READ_4(sc, DC_SIO);
373 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest)
378 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
379 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff;
381 CSR_WRITE_4(sc, DC_ROM, addr | 0x160);
382 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO) & 0xff) << 8;
391 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest)
397 dc_eeprom_idle(sc);
400 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL);
401 dc_delay(sc);
402 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ);
403 dc_delay(sc);
404 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK);
405 dc_delay(sc);
406 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS);
407 dc_delay(sc);
412 dc_eeprom_putbyte(sc, addr);
419 dc_delay(sc);
420 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)
422 dc_delay(sc);
424 dc_delay(sc);
428 dc_eeprom_idle(sc);
437 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt,
444 if (DC_IS_PNIC(sc))
445 dc_eeprom_getword_pnic(sc, off + i, &word);
446 else if (DC_IS_XIRCOM(sc))
447 dc_eeprom_getword_xircom(sc, off + i, &word);
449 dc_eeprom_getword(sc, off + i, &word);
466 dc_mii_writebit(struct dc_softc *sc, int bit)
469 CSR_WRITE_4(sc, DC_SIO,
472 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
474 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
475 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
482 dc_mii_readbit(struct dc_softc *sc)
484 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR);
485 CSR_READ_4(sc, DC_SIO);
486 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK);
487 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK);
488 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN)
497 dc_mii_sync(struct dc_softc *sc)
501 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE);
504 dc_mii_writebit(sc, 1);
511 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt)
516 dc_mii_writebit(sc, bits & i);
523 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame)
540 dc_mii_sync(sc);
545 dc_mii_send(sc, frame->mii_stdelim, 2);
546 dc_mii_send(sc, frame->mii_opcode, 2);
547 dc_mii_send(sc, frame->mii_phyaddr, 5);
548 dc_mii_send(sc, frame->mii_regaddr, 5);
552 dc_mii_writebit(sc, 1);
553 dc_mii_writebit(sc, 0);
557 ack = dc_mii_readbit(sc);
565 dc_mii_readbit(sc);
572 if (dc_mii_readbit(sc))
579 dc_mii_writebit(sc, 0);
580 dc_mii_writebit(sc, 0);
593 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame)
609 dc_mii_sync(sc);
611 dc_mii_send(sc, frame->mii_stdelim, 2);
612 dc_mii_send(sc, frame->mii_opcode, 2);
613 dc_mii_send(sc, frame->mii_phyaddr, 5);
614 dc_mii_send(sc, frame->mii_regaddr, 5);
615 dc_mii_send(sc, frame->mii_turnaround, 2);
616 dc_mii_send(sc, frame->mii_data, 16);
619 dc_mii_writebit(sc, 0);
620 dc_mii_writebit(sc, 0);
630 struct dc_softc *sc = (struct dc_softc *)self;
642 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
650 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
653 if (sc->dc_pmode != DC_PMODE_MII) {
664 if (DC_IS_PNIC(sc))
669 if (DC_IS_PNIC(sc))
681 if (DC_IS_PNIC(sc)) {
682 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ |
686 rval = CSR_READ_4(sc, DC_PN_MII);
695 if (DC_IS_COMET(sc)) {
720 sc->sc_dev.dv_xname, reg);
725 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF;
736 if (sc->dc_type == DC_TYPE_98713) {
737 phy_reg = CSR_READ_4(sc, DC_NETCFG);
738 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
740 dc_mii_readreg(sc, &frame);
741 if (sc->dc_type == DC_TYPE_98713)
742 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
750 struct dc_softc *sc = (struct dc_softc *)self;
756 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR)
758 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR)
761 if (DC_IS_PNIC(sc)) {
762 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE |
765 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY))
771 if (DC_IS_COMET(sc)) {
796 sc->sc_dev.dv_xname, reg);
800 CSR_WRITE_4(sc, phy_reg, data);
808 if (sc->dc_type == DC_TYPE_98713) {
809 phy_reg = CSR_READ_4(sc, DC_NETCFG);
810 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL);
812 dc_mii_writereg(sc, &frame);
813 if (sc->dc_type == DC_TYPE_98713)
814 CSR_WRITE_4(sc, DC_NETCFG, phy_reg);
820 struct dc_softc *sc = (struct dc_softc *)self;
824 if (DC_IS_ADMTEK(sc))
827 mii = &sc->sc_mii;
829 if (DC_IS_DAVICOM(sc) && IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) {
830 dc_setcfg(sc, ifm->ifm_media);
831 sc->dc_if_media = ifm->ifm_media;
833 dc_setcfg(sc, mii->mii_media_active);
834 sc->dc_if_media = mii->mii_media_active;
843 dc_crc_le(struct dc_softc *sc, caddr_t addr)
854 if (sc->dc_flags & DC_128BIT_HASH)
858 if (sc->dc_flags & DC_64BIT_HASH)
863 if (DC_IS_XIRCOM(sc)) {
890 dc_setfilt_21143(struct dc_softc *sc)
892 struct arpcom *ac = &sc->sc_arpcom;
893 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
900 i = sc->dc_cdata.dc_tx_prod;
901 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
902 sc->dc_cdata.dc_tx_cnt++;
903 sframe = &sc->dc_ldata->dc_tx_list[i];
904 sp = &sc->dc_ldata->dc_sbuf[0];
907 sframe->dc_data = htole32(sc->sc_listmap->dm_segs[0].ds_addr +
912 sc->dc_cdata.dc_tx_chain[i].sd_mbuf =
913 (struct mbuf *)&sc->dc_ldata->dc_sbuf[0];
915 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_NETCFG_RX_PROMISC));
921 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
923 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
927 h = dc_crc_le(sc, enm->enm_addrlo);
938 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
942 sp[39] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 0);
943 sp[40] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 1);
944 sp[41] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 2);
946 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
954 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
958 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
972 dc_setfilt_admtek(struct dc_softc *sc)
974 struct arpcom *ac = &sc->sc_arpcom;
975 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
981 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_NETCFG_RX_PROMISC));
988 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
990 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
995 if (DC_IS_CENTAUR(sc))
996 h = dc_crc_le(sc, enm->enm_addrlo);
1010 CSR_WRITE_4(sc, DC_AL_PAR0, ac->ac_enaddr[3] << 24 |
1012 CSR_WRITE_4(sc, DC_AL_PAR1, ac->ac_enaddr[5] << 8 | ac->ac_enaddr[4]);
1014 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]);
1015 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]);
1019 dc_setfilt_asix(struct dc_softc *sc)
1021 struct arpcom *ac = &sc->sc_arpcom;
1022 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1028 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_AX_NETCFG_RX_BROAD |
1036 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD);
1041 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1043 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1060 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0);
1061 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1062 *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[0]));
1063 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1);
1064 CSR_WRITE_4(sc, DC_AX_FILTDATA,
1065 *(u_int32_t *)(&sc->sc_arpcom.ac_enaddr[4]));
1067 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0);
1068 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]);
1069 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1);
1070 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]);
1074 dc_setfilt_xircom(struct dc_softc *sc)
1076 struct arpcom *ac = &sc->sc_arpcom;
1077 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1084 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1086 i = sc->dc_cdata.dc_tx_prod;
1087 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT);
1088 sc->dc_cdata.dc_tx_cnt++;
1089 sframe = &sc->dc_ldata->dc_tx_list[i];
1090 sp = &sc->dc_ldata->dc_sbuf[0];
1093 sframe->dc_data = htole32(sc->sc_listmap->dm_segs[0].ds_addr +
1098 sc->dc_cdata.dc_tx_chain[i].sd_mbuf =
1099 (struct mbuf *)&sc->dc_ldata->dc_sbuf[0];
1101 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ALLMULTI | DC_NETCFG_RX_PROMISC));
1107 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC);
1109 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI);
1114 h = dc_crc_le(sc, enm->enm_addrlo);
1125 h = dc_crc_le(sc, (caddr_t)ðerbroadcastaddr);
1129 sp[0] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 0);
1130 sp[1] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 1);
1131 sp[2] = DC_SP_FIELD(sc->sc_arpcom.ac_enaddr, 2);
1133 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
1134 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
1137 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
1148 dc_setfilt(struct dc_softc *sc)
1150 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) ||
1151 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc))
1152 dc_setfilt_21143(sc);
1154 if (DC_IS_ASIX(sc))
1155 dc_setfilt_asix(sc);
1157 if (DC_IS_ADMTEK(sc))
1158 dc_setfilt_admtek(sc);
1160 if (DC_IS_XIRCOM(sc))
1161 dc_setfilt_xircom(sc);
1170 dc_setcfg(struct dc_softc *sc, uint64_t media)
1178 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) {
1180 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON));
1183 isr = CSR_READ_4(sc, DC_ISR);
1192 if (!(isr & DC_ISR_TX_IDLE) && !DC_IS_ASIX(sc))
1194 sc->sc_dev.dv_xname);
1197 !DC_HAS_BROKEN_RXSTATE(sc))
1199 sc->sc_dev.dv_xname);
1204 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1205 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1206 if (sc->dc_pmode == DC_PMODE_MII) {
1209 if (DC_IS_INTEL(sc)) {
1211 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1214 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1216 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1218 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1220 if (sc->dc_type == DC_TYPE_98713)
1221 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1223 if (!DC_IS_DAVICOM(sc))
1224 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1225 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1226 if (DC_IS_INTEL(sc))
1227 dc_apply_fixup(sc, IFM_AUTO);
1229 if (DC_IS_PNIC(sc)) {
1230 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL);
1231 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1232 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1235 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1236 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1237 if (DC_IS_INTEL(sc))
1238 dc_apply_fixup(sc,
1245 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL);
1246 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT);
1247 if (sc->dc_pmode == DC_PMODE_MII) {
1250 if (DC_IS_INTEL(sc)) {
1252 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG);
1255 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg);
1257 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS);
1259 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS|
1261 if (sc->dc_type == DC_TYPE_98713)
1262 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1263 if (!DC_IS_DAVICOM(sc))
1264 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1265 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1266 if (DC_IS_INTEL(sc))
1267 dc_apply_fixup(sc, IFM_AUTO);
1269 if (DC_IS_PNIC(sc)) {
1270 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL);
1271 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP);
1272 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL);
1274 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1275 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS);
1276 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER);
1277 if (DC_IS_INTEL(sc)) {
1278 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET);
1279 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF);
1281 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D);
1283 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F);
1284 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1285 DC_CLRBIT(sc, DC_10BTCTRL,
1287 dc_apply_fixup(sc,
1300 if (DC_IS_DAVICOM(sc)) {
1302 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1303 sc->dc_link = 1;
1305 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL);
1310 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1311 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1312 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1314 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX);
1315 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc))
1316 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX);
1320 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON);
1324 dc_reset(struct dc_softc *sc)
1328 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1332 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET))
1336 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) ||
1337 DC_IS_INTEL(sc) || DC_IS_CONEXANT(sc)) {
1339 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET);
1344 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
1349 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
1350 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000);
1351 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000);
1359 if (DC_IS_INTEL(sc)) {
1360 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET);
1361 CSR_WRITE_4(sc, DC_10BTCTRL, 0);
1362 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
1365 if (sc->dc_type == DC_TYPE_21145)
1366 dc_setcfg(sc, IFM_10_T);
1370 dc_apply_fixup(struct dc_softc *sc, uint64_t media)
1377 m = sc->dc_mi;
1390 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1395 CSR_WRITE_4(sc, DC_WATCHDOG, reg);
1400 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l)
1439 m->dc_next = sc->dc_mi;
1440 sc->dc_mi = m;
1442 sc->dc_pmode = DC_PMODE_SIA;
1446 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l)
1462 m->dc_next = sc->dc_mi;
1463 sc->dc_mi = m;
1465 sc->dc_pmode = DC_PMODE_SYM;
1469 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l)
1489 m->dc_next = sc->dc_mi;
1490 sc->dc_mi = m;
1494 dc_read_srom(struct dc_softc *sc, int bits)
1496 sc->dc_sromsize = 2 << bits;
1497 sc->dc_srom = malloc(sc->dc_sromsize, M_DEVBUF, M_NOWAIT);
1498 if (sc->dc_srom == NULL)
1500 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (sc->dc_sromsize / 2), 0);
1504 dc_parse_21143_srom(struct dc_softc *sc)
1512 loff = sc->dc_srom[27];
1513 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]);
1539 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr);
1543 dc_decode_leaf_sia(sc,
1548 dc_decode_leaf_sym(sc,
1565 dc_attach(struct dc_softc *sc)
1574 if (sc->sc_hasmac)
1577 switch(sc->dc_type) {
1582 dc_read_eeprom(sc, (caddr_t)&mac_offset,
1584 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
1588 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 0, 3, 1);
1594 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
1599 reg = CSR_READ_4(sc, DC_AL_PAR0);
1600 sc->sc_arpcom.ac_enaddr[0] = (reg & 0xff);
1601 sc->sc_arpcom.ac_enaddr[1] = (reg >> 8) & 0xff;
1602 sc->sc_arpcom.ac_enaddr[2] = (reg >> 16) & 0xff;
1603 sc->sc_arpcom.ac_enaddr[3] = (reg >> 24) & 0xff;
1604 reg = CSR_READ_4(sc, DC_AL_PAR1);
1605 sc->sc_arpcom.ac_enaddr[4] = (reg & 0xff);
1606 sc->sc_arpcom.ac_enaddr[5] = (reg >> 8) & 0xff;
1609 bcopy(&sc->dc_srom + DC_CONEXANT_EE_NODEADDR,
1610 &sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
1614 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 8, 3, 0);
1616 if (sc->sc_arpcom.ac_enaddr[0] == 0x00 &&
1617 sc->sc_arpcom.ac_enaddr[1] == 0x10 &&
1618 sc->sc_arpcom.ac_enaddr[2] == 0xa4)
1620 if (sc->sc_arpcom.ac_enaddr[0] == 0x00 &&
1621 sc->sc_arpcom.ac_enaddr[1] == 0x80 &&
1622 sc->sc_arpcom.ac_enaddr[2] == 0xc7)
1624 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr, 3, 3, 0);
1627 dc_read_eeprom(sc, (caddr_t)&sc->sc_arpcom.ac_enaddr,
1633 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct dc_list_data),
1634 PAGE_SIZE, 0, sc->sc_listseg, 1, &sc->sc_listnseg,
1639 if (bus_dmamem_map(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg,
1640 sizeof(struct dc_list_data), &sc->sc_listkva,
1645 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct dc_list_data), 1,
1647 &sc->sc_listmap) != 0) {
1651 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, sc->sc_listkva,
1656 sc->dc_ldata = (struct dc_list_data *)sc->sc_listkva;
1659 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
1661 &sc->dc_cdata.dc_rx_chain[i].sd_map) != 0) {
1666 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 0,
1667 BUS_DMA_NOWAIT, &sc->sc_rx_sparemap) != 0) {
1673 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1674 (sc->dc_flags & DC_TX_COALESCE) ? 1 : DC_TX_LIST_CNT - 5,
1676 &sc->dc_cdata.dc_tx_chain[i].sd_map) != 0) {
1681 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1682 (sc->dc_flags & DC_TX_COALESCE) ? 1 : DC_TX_LIST_CNT - 5,
1683 MCLBYTES, 0, BUS_DMA_NOWAIT, &sc->sc_tx_sparemap) != 0) {
1691 printf(", address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
1693 ifp = &sc->sc_arpcom.ac_if;
1694 ifp->if_softc = sc;
1700 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
1710 if (DC_IS_INTEL(sc)) {
1711 dc_apply_fixup(sc, IFM_AUTO);
1712 tmp = sc->dc_pmode;
1713 sc->dc_pmode = DC_PMODE_MII;
1721 if (DC_IS_XIRCOM(sc)) {
1722 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
1725 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
1730 sc->sc_mii.mii_ifp = ifp;
1731 sc->sc_mii.mii_readreg = dc_miibus_readreg;
1732 sc->sc_mii.mii_writereg = dc_miibus_writereg;
1733 sc->sc_mii.mii_statchg = dc_miibus_statchg;
1734 ifmedia_init(&sc->sc_mii.mii_media, 0, dc_ifmedia_upd, dc_ifmedia_sts);
1735 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
1738 if (DC_IS_INTEL(sc)) {
1739 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
1740 sc->dc_pmode = tmp;
1741 if (sc->dc_pmode != DC_PMODE_SIA)
1742 sc->dc_pmode = DC_PMODE_SYM;
1743 sc->dc_flags |= DC_21143_NWAY;
1744 if (sc->dc_flags & DC_MOMENCO_BOTCH)
1745 sc->dc_pmode = DC_PMODE_MII;
1746 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff,
1750 sc->dc_flags &= ~DC_TULIP_LEDS;
1754 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
1755 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
1756 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
1757 printf("%s: MII without any PHY!\n", sc->sc_dev.dv_xname);
1758 } else if (sc->dc_type == DC_TYPE_21145) {
1759 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_10_T);
1761 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
1763 if (DC_IS_DAVICOM(sc) && sc->dc_revision >= DC_REVISION_DM9102A)
1764 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_HPNA_1,0,NULL);
1766 if (DC_IS_ADMTEK(sc)) {
1770 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR);
1787 dc_list_tx_init(struct dc_softc *sc)
1794 cd = &sc->dc_cdata;
1795 ld = sc->dc_ldata;
1797 next = sc->sc_listmap->dm_segs[0].ds_addr;
1822 dc_list_rx_init(struct dc_softc *sc)
1829 cd = &sc->dc_cdata;
1830 ld = sc->dc_ldata;
1833 if (dc_newbuf(sc, i, NULL) == ENOBUFS)
1835 next = sc->sc_listmap->dm_segs[0].ds_addr;
1854 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m)
1860 c = &sc->dc_ldata->dc_rx_list[i];
1873 if (bus_dmamap_load_mbuf(sc->sc_dmat, sc->sc_rx_sparemap,
1878 map = sc->dc_cdata.dc_rx_chain[i].sd_map;
1879 sc->dc_cdata.dc_rx_chain[i].sd_map = sc->sc_rx_sparemap;
1880 sc->sc_rx_sparemap = map;
1899 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR)
1902 bus_dmamap_sync(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map, 0,
1903 sc->dc_cdata.dc_rx_chain[i].sd_map->dm_mapsize,
1906 sc->dc_cdata.dc_rx_chain[i].sd_mbuf = m_new;
1908 sc->dc_cdata.dc_rx_chain[i].sd_map->dm_segs[0].ds_addr +
1913 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1975 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx)
1984 i = sc->dc_pnic_rx_bug_save;
1985 cur_rx = &sc->dc_ldata->dc_rx_list[idx];
1986 ptr = sc->dc_pnic_rx_buf;
1991 c = &sc->dc_ldata->dc_rx_list[i];
1993 m = sc->dc_cdata.dc_rx_chain[i].sd_mbuf;
1999 dc_newbuf(sc, i, m);
2016 if (ptr < sc->dc_pnic_rx_buf)
2017 ptr = sc->dc_pnic_rx_buf;
2024 dc_newbuf(sc, i, m);
2041 dc_rx_resync(struct dc_softc *sc)
2046 pos = sc->dc_cdata.dc_rx_prod;
2051 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2055 stat = sc->dc_ldata->dc_rx_list[pos].dc_status;
2066 sc->dc_cdata.dc_rx_prod = pos;
2076 dc_rxeof(struct dc_softc *sc)
2085 ifp = &sc->sc_arpcom.ac_if;
2086 i = sc->dc_cdata.dc_rx_prod;
2092 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2096 cur_rx = &sc->dc_ldata->dc_rx_list[i];
2101 m = sc->dc_cdata.dc_rx_chain[i].sd_mbuf;
2104 bus_dmamap_sync(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map,
2105 0, sc->dc_cdata.dc_rx_chain[i].sd_map->dm_mapsize,
2108 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) {
2111 sc->dc_pnic_rx_bug_save = i;
2116 dc_pnic_rx_bug_war(sc, i);
2122 sc->dc_cdata.dc_rx_chain[i].sd_mbuf = NULL;
2139 dc_newbuf(sc, i, m);
2144 dc_init(sc);
2154 dc_newbuf(sc, i, m);
2166 sc->dc_cdata.dc_rx_prod = i;
2179 dc_txeof(struct dc_softc *sc)
2185 ifp = &sc->sc_arpcom.ac_if;
2191 idx = sc->dc_cdata.dc_tx_cons;
2192 while(idx != sc->dc_cdata.dc_tx_prod) {
2196 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2200 cur_tx = &sc->dc_ldata->dc_tx_list[idx];
2218 if (DC_IS_PNIC(sc)) {
2220 dc_setfilt(sc);
2222 sc->dc_cdata.dc_tx_chain[idx].sd_mbuf = NULL;
2224 sc->dc_cdata.dc_tx_cnt--;
2229 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) {
2238 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2239 sc->dc_pmode == DC_PMODE_MII &&
2244 if (/*sc->dc_type == DC_TYPE_21143 &&*/
2245 sc->dc_pmode == DC_PMODE_MII &&
2258 dc_init(sc);
2265 if (sc->dc_cdata.dc_tx_chain[idx].sd_map->dm_nsegs != 0) {
2266 bus_dmamap_t map = sc->dc_cdata.dc_tx_chain[idx].sd_map;
2268 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2270 bus_dmamap_unload(sc->sc_dmat, map);
2272 if (sc->dc_cdata.dc_tx_chain[idx].sd_mbuf != NULL) {
2273 m_freem(sc->dc_cdata.dc_tx_chain[idx].sd_mbuf);
2274 sc->dc_cdata.dc_tx_chain[idx].sd_mbuf = NULL;
2277 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2281 sc->dc_cdata.dc_tx_cnt--;
2284 sc->dc_cdata.dc_tx_cons = idx;
2286 if (DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt > 5)
2288 if (sc->dc_cdata.dc_tx_cnt == 0)
2295 struct dc_softc *sc = (struct dc_softc *)xsc;
2303 ifp = &sc->sc_arpcom.ac_if;
2304 mii = &sc->sc_mii;
2306 if (sc->dc_flags & DC_REDUCED_MII_POLL) {
2307 if (sc->dc_flags & DC_21143_NWAY) {
2308 r = CSR_READ_4(sc, DC_10BTSTAT);
2311 sc->dc_link = 0;
2316 sc->dc_link = 0;
2319 if (sc->dc_link == 0)
2326 if ((DC_HAS_BROKEN_RXSTATE(sc) || (CSR_READ_4(sc,
2328 sc->dc_cdata.dc_tx_cnt == 0 && !DC_IS_ASIX(sc)) {
2331 sc->dc_link = 0;
2356 if (!sc->dc_link && mii->mii_media_status & IFM_ACTIVE &&
2358 sc->dc_link++;
2363 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link)
2364 timeout_add_msec(&sc->dc_tick_tmo, 100);
2366 timeout_add_sec(&sc->dc_tick_tmo, 1);
2375 dc_tx_underrun(struct dc_softc *sc)
2380 if (DC_IS_DAVICOM(sc))
2381 dc_init(sc);
2383 if (DC_IS_INTEL(sc)) {
2389 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2392 isr = CSR_READ_4(sc, DC_ISR);
2399 sc->sc_dev.dv_xname);
2400 dc_init(sc);
2404 sc->dc_txthresh += DC_TXTHRESH_INC;
2405 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2406 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2408 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2409 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2412 if (DC_IS_INTEL(sc))
2413 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2421 struct dc_softc *sc;
2426 sc = arg;
2428 ifp = &sc->sc_arpcom.ac_if;
2430 ints = CSR_READ_4(sc, DC_ISR);
2438 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS)
2439 dc_stop(sc, 0);
2444 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
2446 while (((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) &&
2451 CSR_WRITE_4(sc, DC_ISR, status);
2454 if (dc_rxeof(sc) == 0) {
2455 while(dc_rx_resync(sc))
2456 dc_rxeof(sc);
2461 dc_txeof(sc);
2464 dc_txeof(sc);
2465 if (sc->dc_cdata.dc_tx_cnt) {
2466 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2467 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2472 dc_tx_underrun(sc);
2476 if (dc_rxeof(sc) == 0) {
2477 while(dc_rx_resync(sc))
2478 dc_rxeof(sc);
2483 dc_init(sc);
2487 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2500 dc_encap(struct dc_softc *sc, bus_dmamap_t map, struct mbuf *m, u_int32_t *idx)
2508 f = &sc->dc_ldata->dc_tx_list[frag];
2521 sc->dc_cdata.dc_tx_cnt += cnt;
2522 sc->dc_cdata.dc_tx_chain[cur].sd_mbuf = m;
2523 sc->sc_tx_sparemap = sc->dc_cdata.dc_tx_chain[cur].sd_map;
2524 sc->dc_cdata.dc_tx_chain[cur].sd_map = map;
2525 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= htole32(DC_TXCTL_LASTFRAG);
2526 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG)
2527 sc->dc_ldata->dc_tx_list[*idx].dc_ctl |=
2529 if (sc->dc_flags & DC_TX_INTR_ALWAYS)
2530 sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
2532 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64)
2533 sc->dc_ldata->dc_tx_list[cur].dc_ctl |=
2535 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
2538 sc->dc_ldata->dc_tx_list[*idx].dc_status = htole32(DC_TXSTAT_OWN);
2553 dc_fits(struct dc_softc *sc, int idx, bus_dmamap_t map)
2555 if (sc->dc_flags & DC_TX_ADMTEK_WAR) {
2556 if (sc->dc_cdata.dc_tx_prod != idx &&
2561 if (sc->dc_cdata.dc_tx_cnt + map->dm_nsegs + 5 > DC_TX_LIST_CNT)
2570 struct dc_softc *sc = ifp->if_softc;
2575 if (!sc->dc_link && ifq_len(&ifp->if_snd) < 10)
2581 idx = sc->dc_cdata.dc_tx_prod;
2583 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2593 map = sc->sc_tx_sparemap;
2594 switch (bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
2600 bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
2612 if (!dc_fits(sc, idx, map)) {
2613 bus_dmamap_unload(sc->sc_dmat, map);
2622 if (dc_encap(sc, map, m, &idx) != 0) {
2637 if (sc->dc_flags & DC_TX_ONE) {
2643 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2648 if (idx == sc->dc_cdata.dc_tx_prod)
2652 sc->dc_cdata.dc_tx_prod = idx;
2653 if (!(sc->dc_flags & DC_TX_POLL))
2654 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF);
2665 struct dc_softc *sc = xsc;
2666 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
2672 mii = &sc->sc_mii;
2677 dc_stop(sc, 0);
2678 dc_reset(sc);
2683 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc))
2684 CSR_WRITE_4(sc, DC_BUSCTL, 0);
2686 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE);
2690 if (DC_IS_INTEL(sc))
2691 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION);
2692 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) {
2693 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA);
2695 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG);
2697 if (sc->dc_flags & DC_TX_POLL)
2698 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1);
2699 switch(sc->dc_cachesize) {
2701 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG);
2704 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG);
2707 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG);
2711 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE);
2715 if (sc->dc_flags & DC_TX_STORENFWD)
2716 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2718 if (sc->dc_txthresh > DC_TXTHRESH_MAX) {
2719 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2721 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD);
2722 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh);
2726 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC);
2727 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF);
2729 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) {
2738 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000);
2739 if (sc->dc_type == DC_TYPE_98713)
2740 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713);
2742 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715);
2745 if (DC_IS_XIRCOM(sc)) {
2746 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN |
2749 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN |
2754 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH);
2755 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN);
2758 if (dc_list_rx_init(sc) == ENOBUFS) {
2760 "memory for rx buffers\n", sc->sc_dev.dv_xname);
2761 dc_stop(sc, 0);
2769 dc_list_tx_init(sc);
2774 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
2775 0, sc->sc_listmap->dm_mapsize,
2781 CSR_WRITE_4(sc, DC_RXADDR, sc->sc_listmap->dm_segs[0].ds_addr +
2783 CSR_WRITE_4(sc, DC_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr +
2789 CSR_WRITE_4(sc, DC_IMR, DC_INTRS);
2790 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF);
2793 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON);
2800 if (sc->dc_flags & DC_TULIP_LEDS) {
2801 CSR_WRITE_4(sc, DC_WATCHDOG,
2803 CSR_WRITE_4(sc, DC_WATCHDOG, 0);
2812 dc_setfilt(sc);
2815 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON);
2816 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF);
2819 dc_setcfg(sc, sc->dc_if_media);
2826 timeout_set(&sc->dc_tick_tmo, dc_tick, sc);
2829 sc->dc_link = 1;
2831 if (sc->dc_flags & DC_21143_NWAY)
2832 timeout_add_msec(&sc->dc_tick_tmo, 100);
2834 timeout_add_sec(&sc->dc_tick_tmo, 1);
2838 if(sc->dc_srm_media) {
2841 ifr.ifr_media = sc->dc_srm_media;
2843 sc->dc_srm_media = 0;
2854 struct dc_softc *sc;
2858 sc = ifp->if_softc;
2859 mii = &sc->sc_mii;
2864 if (DC_IS_DAVICOM(sc) &&
2866 dc_setcfg(sc, ifm->ifm_media);
2868 sc->dc_link = 0;
2879 struct dc_softc *sc;
2883 sc = ifp->if_softc;
2884 mii = &sc->sc_mii;
2887 if (DC_IS_DAVICOM(sc)) {
2901 struct dc_softc *sc = ifp->if_softc;
2911 dc_init(sc);
2918 sc->dc_txthresh = 0;
2919 dc_init(sc);
2923 dc_stop(sc, 0);
2928 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
2930 if (sc->dc_srm_media)
2931 sc->dc_srm_media = 0;
2935 error = ether_ioctl(ifp, &sc->sc_arpcom, command, data);
2940 dc_setfilt(sc);
2951 struct dc_softc *sc;
2953 sc = ifp->if_softc;
2956 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
2958 dc_init(sc);
2969 dc_stop(struct dc_softc *sc, int softonly)
2975 ifp = &sc->sc_arpcom.ac_if;
2978 timeout_del(&sc->dc_tick_tmo);
2984 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON));
2987 isr = CSR_READ_4(sc, DC_ISR);
2998 !DC_IS_ASIX(sc) && !DC_IS_DAVICOM(sc))
3000 sc->sc_dev.dv_xname);
3002 !DC_HAS_BROKEN_RXSTATE(sc))
3004 sc->sc_dev.dv_xname);
3007 CSR_WRITE_4(sc, DC_IMR, 0x00000000);
3008 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000);
3009 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000);
3010 sc->dc_link = 0;
3017 if (sc->dc_cdata.dc_rx_chain[i].sd_map->dm_nsegs != 0) {
3018 bus_dmamap_t map = sc->dc_cdata.dc_rx_chain[i].sd_map;
3020 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
3022 bus_dmamap_unload(sc->sc_dmat, map);
3024 if (sc->dc_cdata.dc_rx_chain[i].sd_mbuf != NULL) {
3025 m_freem(sc->dc_cdata.dc_rx_chain[i].sd_mbuf);
3026 sc->dc_cdata.dc_rx_chain[i].sd_mbuf = NULL;
3029 bzero(&sc->dc_ldata->dc_rx_list, sizeof(sc->dc_ldata->dc_rx_list));
3035 if (sc->dc_cdata.dc_tx_chain[i].sd_map->dm_nsegs != 0) {
3036 bus_dmamap_t map = sc->dc_cdata.dc_tx_chain[i].sd_map;
3038 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
3040 bus_dmamap_unload(sc->sc_dmat, map);
3042 if (sc->dc_cdata.dc_tx_chain[i].sd_mbuf != NULL) {
3043 if (sc->dc_ldata->dc_tx_list[i].dc_ctl &
3045 sc->dc_cdata.dc_tx_chain[i].sd_mbuf = NULL;
3048 m_freem(sc->dc_cdata.dc_tx_chain[i].sd_mbuf);
3049 sc->dc_cdata.dc_tx_chain[i].sd_mbuf = NULL;
3052 bzero(&sc->dc_ldata->dc_tx_list, sizeof(sc->dc_ldata->dc_tx_list));
3054 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
3055 0, sc->sc_listmap->dm_mapsize,
3062 struct dc_softc *sc = (struct dc_softc *)self;
3063 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3068 dc_stop(sc, 0);
3072 dc_init(sc);
3079 dc_detach(struct dc_softc *sc)
3081 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
3084 dc_stop(sc, 1);
3086 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL)
3087 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
3089 if (sc->dc_srom)
3090 free(sc->dc_srom, M_DEVBUF, sc->dc_sromsize);
3093 bus_dmamap_destroy(sc->sc_dmat, sc->dc_cdata.dc_rx_chain[i].sd_map);
3094 if (sc->sc_rx_sparemap)
3095 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_sparemap);
3097 bus_dmamap_destroy(sc->sc_dmat, sc->dc_cdata.dc_tx_chain[i].sd_map);
3098 if (sc->sc_tx_sparemap)
3099 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_sparemap);
3102 bus_dmamap_unload(sc->sc_dmat, sc->sc_listmap);
3103 bus_dmamem_unmap(sc->sc_dmat, sc->sc_listkva, sc->sc_listnseg);
3104 bus_dmamap_destroy(sc->sc_dmat, sc->sc_listmap);
3105 bus_dmamem_free(sc->sc_dmat, sc->sc_listseg, sc->sc_listnseg);