Lines Matching defs:ath_stats
73 struct ath_stats { struct
74 u_int32_t ast_watchdog; /* device reset by watchdog */
75 u_int32_t ast_hardware; /* fatal hardware error interrupts */
76 u_int32_t ast_bmiss; /* beacon miss interrupts */
77 u_int32_t ast_mib; /* MIB counter interrupts */
78 u_int32_t ast_rxorn; /* rx overrun interrupts */
79 u_int32_t ast_rxeol; /* rx eol interrupts */
80 u_int32_t ast_txurn; /* tx underrun interrupts */
81 u_int32_t ast_intrcoal; /* interrupts coalesced */
82 u_int32_t ast_tx_mgmt; /* management frames transmitted */
83 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */
84 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */
85 u_int32_t ast_tx_encap; /* tx encapsulation failed */
86 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */
87 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */
88 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */
89 u_int32_t ast_tx_linear; /* tx linearized to cluster */
90 u_int32_t ast_tx_nodata; /* tx discarded empty frame */
91 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
92 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */
93 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */
94 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */
95 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
96 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
97 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */
98 u_int32_t ast_tx_noack; /* tx frames with no ack marked */
99 u_int32_t ast_tx_rts; /* tx frames with rts enabled */
100 u_int32_t ast_tx_cts; /* tx frames with cts enabled */
101 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */
102 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */
103 u_int32_t ast_tx_protect; /* tx frames with protection */
104 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */
105 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
106 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */
107 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */
108 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */
109 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */
110 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */
111 u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */
112 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */
113 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */
114 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */
115 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */
116 u_int32_t ast_per_cal; /* periodic calibration calls */
117 u_int32_t ast_per_calfail;/* periodic calibration failed */
118 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */
119 u_int32_t ast_rate_calls; /* rate control checks */
120 u_int32_t ast_rate_raise; /* rate control raised xmit rate */
121 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */