196 struct ath_softc {  struct
199 	int			(*sc_enable)(struct ath_softc *);  argument
200 	void			(*sc_disable)(struct ath_softc *);  argument
201 	void			(*sc_power)(struct ath_softc *, int);  argument
202 	int			(*sc_newstate)(struct ieee80211com *,
204 	void			(*sc_node_free)(struct ieee80211com *,
206 	void			(*sc_node_copy)(struct ieee80211com *,
209 	void			(*sc_recv_mgmt)(struct ieee80211com *,
212 	bus_space_tag_t		sc_st;		/* bus space tag */
213 	bus_space_handle_t	sc_sh;		/* bus space handle */
214 	bus_size_t		sc_ss;		/* bus space size */
215 	bus_dma_tag_t		sc_dmat;	/* bus DMA tag */
216 	struct ath_hal		*sc_ah;		/* Atheros HAL */
217 	unsigned int		sc_invalid : 1,	/* disable hardware accesses */
218 				sc_doani : 1,	/* dynamic noise immunity */
219 				sc_veol : 1,	/* tx VEOL support */
220 				sc_softled : 1,	/* GPIO software LED */
221 				sc_probing : 1,	/* probing AP on beacon miss */
222 				sc_pcie : 1;	/* indicates PCI Express */
223 	u_int			sc_nchan;	/* number of valid channels */
224 	const HAL_RATE_TABLE	*sc_rates[IEEE80211_MODE_MAX];
225 	const HAL_RATE_TABLE	*sc_currates;	/* current rate table */
226 	enum ieee80211_phymode	sc_curmode;	/* current phy mode */
227 	u_int8_t		sc_rixmap[256];	/* IEEE to h/w rate table ix */
228 	u_int8_t		sc_hwmap[32];	/* h/w rate ix to IEEE table */
229 	HAL_INT			sc_imask;	/* interrupt mask copy */
232 	caddr_t			sc_drvbpf;
234 	union {
237 	}			sc_rxtapu;
239 	int			sc_rxtap_len;
241 	union {
244 	}			sc_txtapu;
246 	int			sc_txtap_len;
249 	struct ath_desc		*sc_desc;	/* TX/RX descriptors */
250 	bus_dma_segment_t	sc_dseg;
251 	int			sc_dnseg;	/* number of segments */
252 	bus_dmamap_t		sc_ddmamap;	/* DMA map for descriptors */
253 	bus_addr_t		sc_desc_paddr;	/* physical addr of sc_desc */
254 	bus_addr_t		sc_desc_len;	/* size of sc_desc */
256 	ath_task_t		sc_fataltask;	/* fatal int processing */
257 	ath_task_t		sc_rxorntask;	/* rxorn int processing */
260 	u_int32_t		*sc_rxlink;	/* link ptr in last RX desc */
261 	ath_task_t		sc_rxtask;	/* rx int processing */
263 	u_int			sc_txhalq[HAL_NUM_TX_QUEUES];	/* HAL q for outgoing frames */
264 	u_int32_t		*sc_txlink;	/* link ptr in last TX desc */
265 	int			sc_tx_timer;	/* transmit timeout */
268 	ath_task_t		sc_txtask;	/* tx int processing */
270 	u_int			sc_bhalq;	/* HAL q for outgoing beacons */
271 	struct ath_buf		*sc_bcbuf;	/* beacon buffer */
272 	struct ath_buf		*sc_bufptr;	/* allocated buffer ptr */
273 	ath_task_t		sc_swbatask;	/* swba int processing */
274 	ath_task_t		sc_bmisstask;	/* bmiss int processing */
276 	struct timeval		sc_last_ch;
277 	struct timeout		sc_cal_to;
278 	struct timeval		sc_last_beacon;
279 	struct timeout		sc_scan_to;
280 	struct timeout		sc_rssadapt_to;
281 	struct ath_stats	sc_stats;	/* interface statistics */
282 	HAL_MIB_STATS		sc_mib_stats;	/* MIB counter statistics */
284 	u_int			sc_flags;	/* misc flags */
286 	u_int8_t                sc_broadcast_addr[IEEE80211_ADDR_LEN];
288 	struct gpio_chipset_tag sc_gpio_gc;	/* gpio(4) framework */
289 	gpio_pin_t		sc_gpio_pins[ATH_MAXGPIO];