Lines Matching defs:ar5k_eeprom_info

723 struct ar5k_eeprom_info {  struct
724 	u_int16_t	ee_magic;
725 	u_int16_t	ee_protect;
726 	u_int16_t	ee_regdomain;
727 	u_int16_t	ee_version;
728 	u_int16_t	ee_header;
729 	u_int16_t	ee_ant_gain;
730 	u_int16_t	ee_misc0;
731 	u_int16_t	ee_misc1;
732 	u_int16_t	ee_cck_ofdm_gain_delta;
733 	u_int16_t	ee_cck_ofdm_power_delta;
734 	u_int16_t	ee_scaled_cck_delta;
735 	u_int16_t	ee_tx_clip;
736 	u_int16_t	ee_pwd_84;
737 	u_int16_t	ee_pwd_90;
738 	u_int16_t	ee_gain_select;
740 	u_int16_t	ee_i_cal[AR5K_EEPROM_N_MODES];
741 	u_int16_t	ee_q_cal[AR5K_EEPROM_N_MODES];
742 	u_int16_t	ee_fixed_bias[AR5K_EEPROM_N_MODES];
743 	u_int16_t	ee_xr_power[AR5K_EEPROM_N_MODES];
744 	u_int16_t	ee_switch_settling[AR5K_EEPROM_N_MODES];
745 	u_int16_t	ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
746 	u_int16_t	ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
747 	u_int16_t	ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
748 	u_int16_t	ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
749 	u_int16_t	ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
750 	u_int16_t	ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
751 	u_int16_t	ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
752 	u_int16_t	ee_thr_62[AR5K_EEPROM_N_MODES];
753 	u_int16_t	ee_xlna_gain[AR5K_EEPROM_N_MODES];
754 	u_int16_t	ee_xpd[AR5K_EEPROM_N_MODES];
755 	u_int16_t	ee_x_gain[AR5K_EEPROM_N_MODES];
756 	u_int16_t	ee_i_gain[AR5K_EEPROM_N_MODES];
757 	u_int16_t	ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
758 	u_int16_t	ee_false_detect[AR5K_EEPROM_N_MODES];
759 	u_int16_t	ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
760 	u_int16_t	ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN];
762 	u_int16_t	ee_ctls;
763 	u_int16_t	ee_ctl[AR5K_EEPROM_MAX_CTLS];
765 	int16_t		ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
766 	int8_t		ee_adc_desired_size[AR5K_EEPROM_N_MODES];
767 	int8_t		ee_pga_desired_size[AR5K_EEPROM_N_MODES];