Lines Matching defs:xa
1764 struct ata_xfer *xa = &ccb->ccb_xa;
1770 if (xa->datalen == 0) {
1775 error = bus_dmamap_load(sc->sc_dmat, dmap, xa->data, xa->datalen, NULL,
1776 (xa->flags & ATA_F_NOWAIT) ? BUS_DMA_NOWAIT : BUS_DMA_WAITOK);
1789 ISSET(xa->flags, ATA_F_PIO) ? AHCI_PRDT_FLAG_INTR : 0);
1794 (xa->flags & ATA_F_READ) ? BUS_DMASYNC_PREREAD :
1805 struct ata_xfer *xa = &ccb->ccb_xa;
1808 if (xa->datalen != 0) {
1810 (xa->flags & ATA_F_READ) ? BUS_DMASYNC_POSTREAD :
1816 xa->resid = 0;
1818 xa->resid = xa->datalen -
2809 ahci_ata_put_xfer(struct ata_xfer *xa)
2811 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
2819 ahci_ata_cmd(struct ata_xfer *xa)
2821 struct ahci_ccb *ccb = (struct ahci_ccb *)xa;
2833 flags |= xa->pmp_port << AHCI_CMD_LIST_FLAG_PMP_SHIFT;
2835 if (xa->flags & ATA_F_WRITE)
2838 if (xa->flags & ATA_F_PACKET)
2846 timeout_set(&xa->stimeout, ahci_ata_cmd_timeout, ccb);
2848 xa->state = ATA_S_PENDING;
2850 if (xa->flags & ATA_F_POLL)
2851 ahci_poll(ccb, xa->timeout, ahci_ata_cmd_timeout);
2854 timeout_add_msec(&xa->stimeout, xa->timeout);
2863 xa->state = ATA_S_ERROR;
2864 ata_complete(xa);
2871 struct ata_xfer *xa = &ccb->ccb_xa;
2873 if (xa->state == ATA_S_ONCHIP || xa->state == ATA_S_ERROR)
2875 xa->flags & ATA_F_NCQ);
2877 xa->state = ATA_S_COMPLETE;
2884 struct ata_xfer *xa = &ccb->ccb_xa;
2886 timeout_del(&xa->stimeout);
2888 if (xa->state == ATA_S_ONCHIP || xa->state == ATA_S_ERROR)
2890 xa->flags & ATA_F_NCQ);
2894 if (xa->state == ATA_S_ONCHIP)
2895 xa->state = ATA_S_COMPLETE;
2897 else if (xa->state != ATA_S_ERROR && xa->state != ATA_S_TIMEOUT)
2899 "slot %d\n", PORTNAME(ccb->ccb_port), xa->state,
2902 if (xa->state != ATA_S_TIMEOUT)
2903 ata_complete(xa);
2910 struct ata_xfer *xa = &ccb->ccb_xa;
2917 ncq_cmd = (xa->flags & ATA_F_NCQ);
2960 ncq_cmd ? " NCQ" : "", ccb->ccb_slot, xa->pmp_port, *active);
2988 ata_complete(xa);
3180 struct ata_xfer *xa = &ccb->ccb_xa;
3190 if (xa->datalen == 0) {
3199 buflen = xa->datalen;
3200 data_addr = (vaddr_t)xa->data;