Lines Matching defs:div_con

498 	uint32_t parent_freq, div, div_con, max_div_con;
506 	div_con = (div > 0 ? div - 1 : 0);
507 	return (div_con < max_div_con) ? div_con : max_div_con;
514 	uint32_t parent_freq, div_con;
518 	div_con = rkclock_div_con(sc, clk, mux, freq);
519 	return parent_freq / (div_con + 1);
526 	uint32_t reg, mux, div_con;
543 		div_con = 0;
545 		div_con = (reg & clk->div_mask) >> shift;
552 	return sc->sc_cd.cd_get_frequency(sc, &idx) / (div_con + 1);
559 	uint32_t reg, mux, div_con;
645 	div_con = rkclock_div_con(sc, clk, best_mux, freq);
649 	    clk->div_mask << 16 | div_con << div_shift);
820 	uint32_t reg, mux, div_con, aclk_div_con;
834 		div_con = (reg >> 8) & 0x1f;
836 		return rk3288_get_frequency(sc, &idx) / (div_con + 1);
842 		div_con = reg & 0x7f;
844 			return 24000000 / (div_con + 1);
849 		div_con = reg & 0x7f;
851 			return 24000000 / (div_con + 1);
856 		div_con = reg & 0x7f;
858 			return 24000000 / (div_con + 1);
863 		div_con = reg & 0x7f;
865 			return 24000000 / (div_con + 1);
870 		div_con = reg & 0x7f;
872 			return 24000000 / (div_con + 1);
879 		div_con = (reg >> 8) & 0x1f;
893 		return rk3288_get_frequency(sc, &idx) / (div_con + 1);
899 		div_con = (reg >> 12) & 0x7;
904 		return rk3288_get_frequency(sc, &idx) / (div_con + 1);
912 		div_con = (reg >> 12) & 0x3;
920 		    div_con;
1163 	uint32_t reg, mux, div_con;
1169 	div_con = (reg & RK3308_CRU_CLK_CORE_DIV_CON_MASK) >>
1173 	return rk3308_get_frequency(sc, &idx) / (div_con + 1);
1399 	uint32_t reg, mux, pll, div_con;
1413 	div_con = HREAD4(sc, RK3308_CRU_CLKSEL_CON(4)) & 0xffff;
1414 	return rk3308_get_frequency(sc, &pll) / (div_con + 1);
1421 	uint32_t vpll0_freq, vpll1_freq, mux, div_con;
1435 	div_con = rkclock_div_con(sc, clk, mux, freq);
1437 	HWRITE4(sc, RK3308_CRU_CLKSEL_CON(4), 0xffff0000 | div_con);
1779 	uint32_t reg, mux, div_con;
1785 	div_con = (reg & RK3328_CRU_CLK_CORE_DIV_CON_MASK) >>
1789 	return rk3328_get_frequency(sc, &idx) / (div_con + 1);
2731 	uint32_t reg, mux, div_con;
2737 	div_con = (reg & RK3399_CRU_CLK_CORE_DIV_CON_MASK) >>
2741 	return rk3399_get_frequency(sc, &idx) / (div_con + 1);