Lines Matching full:data
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
159 int offset, pcireg_t *data) in glx_pci_read_hook() argument
173 *data = 0; in glx_pci_read_hook()
177 *data = glx_fn0_read(offset); in glx_pci_read_hook()
182 *data = glx_fn2_read(offset); in glx_pci_read_hook()
185 *data = glx_fn3_read(offset); in glx_pci_read_hook()
188 *data = glx_fn4_read(offset); in glx_pci_read_hook()
191 *data = glx_fn5_read(offset); in glx_pci_read_hook()
204 int offset, pcireg_t data) in glx_pci_write_hook() argument
220 glx_fn0_write(offset, data); in glx_pci_write_hook()
225 glx_fn2_write(offset, data); in glx_pci_write_hook()
228 glx_fn3_write(offset, data); in glx_pci_write_hook()
231 glx_fn4_write(offset, data); in glx_pci_write_hook()
234 glx_fn5_write(offset, data); in glx_pci_write_hook()
249 pcireg_t data; in glx_get_status() local
251 data = 0; in glx_get_status()
254 data |= PCI_COMMAND_PARITY_ENABLE; in glx_get_status()
255 data |= PCI_STATUS_66MHZ_SUPPORT | in glx_get_status()
258 data |= PCI_STATUS_PARITY_DETECT; in glx_get_status()
260 data |= PCI_STATUS_TARGET_TARGET_ABORT; in glx_get_status()
262 data |= PCI_STATUS_MASTER_TARGET_ABORT; in glx_get_status()
264 data |= PCI_STATUS_MASTER_ABORT; in glx_get_status()
266 return data; in glx_get_status()
297 pcireg_t data; in glx_fn0_read() local
303 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_PCIB); in glx_fn0_read()
306 data = glx_get_status(); in glx_fn0_read()
307 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn0_read()
310 data |= PCI_COMMAND_IO_ENABLE; in glx_fn0_read()
314 data = (PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT) | in glx_fn0_read()
320 data = (0x80 << PCI_HDRTYPE_SHIFT) | in glx_fn0_read()
333 data = 0; in glx_fn0_read()
335 data = pcib_bar_values[index]; in glx_fn0_read()
336 if (data == 0xffffffff) in glx_fn0_read()
337 data = PCI_MAPREG_IO_ADDR_MASK; in glx_fn0_read()
339 data = (pcireg_t)rdmsr(pcib_bar_msr[index]); in glx_fn0_read()
340 data &= ~(pcib_bar_sizes[index] - 1); in glx_fn0_read()
341 if (data != 0) in glx_fn0_read()
342 data |= PCI_MAPREG_TYPE_IO; in glx_fn0_read()
346 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn0_read()
350 data = 0; in glx_fn0_read()
354 return data; in glx_fn0_read()
358 glx_fn0_write(int reg, pcireg_t data) in glx_fn0_write() argument
369 if (data & PCI_COMMAND_IO_ENABLE) in glx_fn0_write()
377 if (data & PCI_COMMAND_PARITY_ENABLE) in glx_fn0_write()
386 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn0_write()
396 if (data == 0xffffffff) { in glx_fn0_write()
397 pcib_bar_values[index] = data; in glx_fn0_write()
399 if ((data & PCI_MAPREG_TYPE_MASK) == in glx_fn0_write()
401 data &= PCI_MAPREG_IO_ADDR_MASK; in glx_fn0_write()
402 data &= ~(pcib_bar_sizes[index] - 1); in glx_fn0_write()
404 (0x0000f000UL << 32) | (1UL << 32) | data); in glx_fn0_write()
425 pcireg_t data; in glx_fn2_read() local
430 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_IDE); in glx_fn2_read()
433 data = glx_get_status(); in glx_fn2_read()
434 data |= PCI_COMMAND_IO_ENABLE; in glx_fn2_read()
437 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn2_read()
441 data = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) | in glx_fn2_read()
448 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn2_read()
453 data = pciide_bar_value; in glx_fn2_read()
454 if (data == 0xffffffff) in glx_fn2_read()
455 data = PCI_MAPREG_IO_ADDR_MASK & ~(pciide_bar_size - 1); in glx_fn2_read()
458 data = msr & 0xfffffff0; in glx_fn2_read()
460 if (data != 0) in glx_fn2_read()
461 data |= PCI_MAPREG_TYPE_IO; in glx_fn2_read()
465 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn2_read()
472 data = rdmsr(IDE_CFG); in glx_fn2_read()
475 data = rdmsr(IDE_DTC); in glx_fn2_read()
478 data = rdmsr(IDE_ETC); in glx_fn2_read()
481 data = 0; in glx_fn2_read()
485 return data; in glx_fn2_read()
489 glx_fn2_write(int reg, pcireg_t data) in glx_fn2_write() argument
496 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn2_write()
505 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn2_write()
508 if (data == 0xffffffff) { in glx_fn2_write()
509 pciide_bar_value = data; in glx_fn2_write()
511 if ((data & PCI_MAPREG_TYPE_MASK) == in glx_fn2_write()
513 data &= PCI_MAPREG_IO_ADDR_MASK; in glx_fn2_write()
514 msr = (uint32_t)data & 0xfffffff0; in glx_fn2_write()
526 wrmsr(IDE_CFG, (uint32_t)data); in glx_fn2_write()
529 wrmsr(IDE_DTC, (uint32_t)data); in glx_fn2_write()
532 wrmsr(IDE_ETC, (uint32_t)data); in glx_fn2_write()
548 pcireg_t data; in glx_fn3_read() local
553 data = PCI_ID_CODE(PCI_VENDOR_AMD, in glx_fn3_read()
557 data = glx_get_status(); in glx_fn3_read()
558 data |= PCI_COMMAND_IO_ENABLE; in glx_fn3_read()
561 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn3_read()
565 data = (PCI_CLASS_MULTIMEDIA << PCI_CLASS_SHIFT) | in glx_fn3_read()
571 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn3_read()
576 data = ac97_bar_value; in glx_fn3_read()
577 if (data == 0xffffffff) in glx_fn3_read()
578 data = PCI_MAPREG_IO_ADDR_MASK & ~(ac97_bar_size - 1); in glx_fn3_read()
581 data = (msr >> 20) & 0x000fffff; in glx_fn3_read()
582 data &= (msr & 0x000fffff); in glx_fn3_read()
584 if (data != 0) in glx_fn3_read()
585 data |= PCI_MAPREG_TYPE_IO; in glx_fn3_read()
588 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn3_read()
592 data = 0; in glx_fn3_read()
596 return data; in glx_fn3_read()
600 glx_fn3_write(int reg, pcireg_t data) in glx_fn3_write() argument
607 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn3_write()
616 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn3_write()
619 if (data == 0xffffffff) { in glx_fn3_write()
620 ac97_bar_value = data; in glx_fn3_write()
622 if ((data & PCI_MAPREG_TYPE_MASK) == in glx_fn3_write()
624 data &= PCI_MAPREG_IO_ADDR_MASK; in glx_fn3_write()
628 msr |= ((uint64_t)data & 0xfffff) << 20; in glx_fn3_write()
651 pcireg_t data; in glx_fn4_read() local
656 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_OHCI); in glx_fn4_read()
659 data = glx_get_status(); in glx_fn4_read()
662 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn4_read()
664 data |= PCI_COMMAND_MEM_ENABLE; in glx_fn4_read()
668 data = (PCI_CLASS_SERIALBUS << PCI_CLASS_SHIFT) | in glx_fn4_read()
675 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn4_read()
680 data = ohci_bar_value; in glx_fn4_read()
681 if (data == 0xffffffff) in glx_fn4_read()
682 data = PCI_MAPREG_MEM_ADDR_MASK & ~(ohci_bar_size - 1); in glx_fn4_read()
685 data = msr & 0xffffff00; in glx_fn4_read()
687 if (data != 0) in glx_fn4_read()
688 data |= PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT; in glx_fn4_read()
691 data = 0x40; in glx_fn4_read()
694 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn4_read()
698 data = 0; in glx_fn4_read()
701 data = 0; in glx_fn4_read()
705 return data; in glx_fn4_read()
709 glx_fn4_write(int reg, pcireg_t data) in glx_fn4_write() argument
716 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn4_write()
720 if (data & PCI_COMMAND_MEM_ENABLE) in glx_fn4_write()
729 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn4_write()
732 if (data == 0xffffffff) { in glx_fn4_write()
733 ohci_bar_value = data; in glx_fn4_write()
735 if ((data & PCI_MAPREG_TYPE_MASK) == in glx_fn4_write()
737 data &= PCI_MAPREG_MEM_ADDR_MASK; in glx_fn4_write()
741 msr |= (((uint64_t)data) >> 12) << 20; in glx_fn4_write()
747 msr |= data; in glx_fn4_write()
772 pcireg_t data; in glx_fn5_read() local
777 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_EHCI); in glx_fn5_read()
780 data = glx_get_status(); in glx_fn5_read()
783 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn5_read()
785 data |= PCI_COMMAND_MEM_ENABLE; in glx_fn5_read()
789 data = (PCI_CLASS_SERIALBUS << PCI_CLASS_SHIFT) | in glx_fn5_read()
796 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn5_read()
801 data = ehci_bar_value; in glx_fn5_read()
802 if (data == 0xffffffff) in glx_fn5_read()
803 data = PCI_MAPREG_MEM_ADDR_MASK & ~(ehci_bar_size - 1); in glx_fn5_read()
806 data = msr & 0xffffff00; in glx_fn5_read()
808 if (data != 0) in glx_fn5_read()
809 data |= PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT; in glx_fn5_read()
812 data = 0x40; in glx_fn5_read()
815 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn5_read()
819 data = 0; in glx_fn5_read()
823 data = PCI_USBREV_2_0; in glx_fn5_read()
824 data |= ((msr >> 40) & 0x3f) << 8; /* PCI_EHCI_FLADJ */ in glx_fn5_read()
827 data = 0; in glx_fn5_read()
831 return data; in glx_fn5_read()
835 glx_fn5_write(int reg, pcireg_t data) in glx_fn5_write() argument
842 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn5_write()
846 if (data & PCI_COMMAND_MEM_ENABLE) in glx_fn5_write()
855 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn5_write()
858 if (data == 0xffffffff) { in glx_fn5_write()
859 ehci_bar_value = data; in glx_fn5_write()
861 if ((data & PCI_MAPREG_TYPE_MASK) == in glx_fn5_write()
863 data &= PCI_MAPREG_MEM_ADDR_MASK; in glx_fn5_write()
867 msr |= (((uint64_t)data) >> 12) << 20; in glx_fn5_write()
873 msr |= data; in glx_fn5_write()