Lines Matching full:set
1 ; Hitachi SHcompact instruction set description. -*- Scheme -*-
88 (set (index newval) (set (reg h-fr (add (front) index)) newval))
98 (set (index newval) (set (reg h-dr (add (front) index)) newval))
108 (set (index newval) (set (reg h-fr (add (back) index)) newval))
118 (set (index newval) (set (reg h-dr (add (back) index)) newval))
128 (set (index newval) (set (reg h-fr (add (front) index)) newval))
137 (set (newvalue) (sequence ()
138 (set (reg h-fpscr) newvalue)
139 (set prbit (and (srl newvalue 19) 1))
140 (set szbit (and (srl newvalue 20) 1))
141 (set frbit (and (srl newvalue 21) 1))))
150 (set (newval) (set (raw-reg h-gr 16) (ext DI newval)))
159 (set (newval) (set (raw-reg h-gr 18) (ext DI newval)))
168 (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval)))
177 (set (newval) (set (raw-reg h-gr 17) (-join-si newval (subword SI (raw-reg h-gr 17) 1))))
186 (set (newval) (set (raw-reg h-gr 19) (or (and (raw-reg h-gr 19) (inv DI 1)) (zext DI newval))))
330 (set rn (add rn rm)))
336 (set rn (add rn (ext SI (and QI imm8 255)))))
343 (set flag (add-cflag rn rm tbit))
344 (set rn (addc rn rm tbit))
345 (set tbit flag)))
352 (set t (add-oflag rn rm 0))
353 (set rn (add rn rm))
354 (set tbit t)))
360 (set rn64 (and rm64 rn64)))
366 (set r0 (and r0 (zext DI uimm8))))
373 (set addr (add r0 gbr))
374 (set data (and (mem UQI addr) imm8))
375 (set (mem UQI addr) data)))
382 (set pc disp8)))
389 (delay 1 (set pc disp8))))
395 (delay 1 (set pc disp12)))
401 (delay 1 (set pc (add (ext DI rn) (add pc 4)))))
414 (set pr (add pc 4))
415 (set pc disp12))))
422 (set pr (add pc 4))
423 (set pc (add (ext DI rn) (add pc 4))))))
430 (set pc disp8)))
437 (delay 1 (set pc disp8))))
444 (set macl 0)
445 (set mach 0)))
451 (set sbit 0))
457 (set tbit 0))
463 (set tbit (eq rm rn)))
469 (set tbit (eq r0 (ext SI (and QI imm8 255)))))
475 (set tbit (ge rn rm)))
481 (set tbit (gt rn rm)))
487 (set tbit (gtu rn rm)))
493 (set tbit (geu rn rm)))
499 (set tbit (gt rn 0)))
505 (set tbit (ge rn 0)))
512 (set temp (xor rm rn))
513 (set t (eq (and temp #xff000000) 0))
514 (set t (or (eq (and temp #xff0000) 0) t))
515 (set t (or (eq (and temp #xff00) 0) t))
516 (set t (or (eq (and temp #xff) 0) t))
517 (set tbit (if BI (gtu t 0) 1 0))))
524 (set qbit (srl rn 31))
525 (set mbit (srl rm 31))
526 (set tbit (if BI (eq (srl rm 31) (srl rn 31)) 0 1))))
533 (set tbit 0)
534 (set qbit 0)
535 (set mbit 0)))
542 (set oldq qbit)
543 (set qbit (srl rn 31))
544 (set rn (or (sll rn 1) (zext SI tbit)))
548 (set tmp0 rn)
549 (set rn (sub rn rm))
550 (set tmp1 (gtu rn tmp0))
552 (set qbit (if BI tmp1 1 0))
553 (set qbit (if BI (eq tmp1 0) 1 0))))
555 (set tmp0 rn)
556 (set rn (add rn rm))
557 (set tmp1 (ltu rn tmp0))
559 (set qbit (if BI (eq tmp1 0) 1 0))
560 (set qbit (if BI tmp1 1 0)))))
563 (set tmp0 rn)
564 (set rn (add rm rn))
565 (set tmp1 (ltu rn tmp0))
567 (set qbit (if BI tmp1 1 0))
568 (set qbit (if BI (eq tmp1 0) 1 0))))
570 (set tmp0 rn)
571 (set rn (sub rn rm))
572 (set tmp1 (gtu rn tmp0))
574 (set qbit (if BI (eq tmp1 0) 1 0))
575 (set qbit (if BI tmp1 1 0))))))
576 (set tbit (if BI (eq qbit mbit) 1 0))))
583 (set result (mul (ext DI rm) (ext DI rn)))
584 (set mach (subword SI result 0))
585 (set macl (subword SI result 1))))
592 (set result (mul (zext DI rm) (zext DI rn)))
593 (set mach (subword SI result 0))
594 (set macl (subword SI result 1))))
596 (dshci dt "Decrement and set"
601 (set rn (sub rn 1))
602 (set tbit (eq rn 0))))
608 (set rn (ext SI (subword QI rm 3))))
614 (set rn (ext SI (subword HI rm 1))))
620 (set rn (zext SI (subword QI rm 3))))
626 (set rn (zext SI (subword HI rm 1))))
633 (set (dr fsdn) (c-call DF "sh64_fabsd" (dr fsdn)))
634 (set fsdn (c-call SF "sh64_fabss" fsdn))))
641 (set (dr fsdn) (c-call DF "sh64_faddd" (dr fsdm) (dr fsdn)))
642 (set fsdn (c-call SF "sh64_fadds" fsdm fsdn))))
649 (set tbit (c-call BI "sh64_fcmpeqd" (dr fsdm) (dr fsdn)))
650 (set tbit (c-call BI "sh64_fcmpeqs" fsdm fsdn))))
657 (set tbit (c-call BI "sh64_fcmpgtd" (dr fsdn) (dr fsdm)))
658 (set tbit (c-call BI "sh64_fcmpgts" fsdn fsdm))))
664 (set fpul (c-call SF "sh64_fcnvds" drn)))
670 (set drn (c-call DF "sh64_fcnvsd" fpul)))
677 (set (dr fsdn) (c-call DF "sh64_fdivd" (dr fsdn) (dr fsdm)))
678 (set fsdn (c-call SF "sh64_fdivs" fsdn fsdm))))
685 (set m (index-of fvm))
686 (set n (index-of fvn))
687 (set res (c-call SF "sh64_fmuls" fvm fvn))
688 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 1)) (reg h-frc (add…
689 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 2)) (reg h-frc (add…
690 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-frc (add m 3)) (reg h-frc (add…
691 (set (reg h-frc (add n 3)) res)))
697 (set fpul frn))
703 (set frn (c-call SF "sh64_fldi0")))
709 (set frn (c-call SF "sh64_fldi1")))
716 (set (dr fsdn) (c-call DF "sh64_floatld" fpul))
717 (set fsdn (c-call SF "sh64_floatls" fpul))))
723 (set frn (c-call SF "sh64_fmacs" (reg h-frc 0) frm frn)))
735 (set frn frm)
739 (set (xd frn) (xd frm))
740 (set (dr frn) (xd frm)))
742 (set (xd frn) (dr frm))
743 (set (dr frn) (dr frm))))))
751 (set frn (mem SF rm))
754 (set (xd frn) (mem DF rm))
755 (set (dr frn) (mem DF rm)))))
764 (set frn (mem SF rm))
765 (set rm (add rm 4)))
769 (set (xd frn) (mem DF rm))
770 (set (dr frn) (mem DF rm)))
771 (set rm (add rm 8)))))
779 (set frn (mem SF (add r0 rm)))
782 (set (xd frn) (mem DF (add r0 rm)))
783 (set (dr frn) (mem DF (add r0 rm))))))
791 (set (mem SF rn) frm)
794 (set (mem DF rn) (xd frm))
795 (set (mem DF rn) (dr frm)))))
804 (set rn (sub rn 4))
805 (set (mem SF rn) frm))
808 (set rn (sub rn 8))
810 (set (mem DF rn) (xd frm))
811 (set (mem DF rn) (dr frm))))))
819 (set (mem SF (add r0 rn)) frm)
822 (set (mem DF (add r0 rn)) (xd frm))
823 (set (mem DF (add r0 rn)) (dr frm)))))
830 (set (dr fsdn) (c-call DF "sh64_fmuld" (dr fsdm) (dr fsdn)))
831 (set fsdn (c-call SF "sh64_fmuls" fsdm fsdn))))
838 (set (dr fsdn) (c-call DF "sh64_fnegd" (dr fsdn)))
839 (set fsdn (c-call SF "sh64_fnegs" fsdn))))
845 (set frbit (not frbit)))
847 (dshci fschg "Set size of floating point transfers"
851 (set szbit (not szbit)))
858 (set (dr fsdn) (c-call DF "sh64_fsqrtd" (dr fsdn)))
859 (set fsdn (c-call SF "sh64_fsqrts" fsdn))))
865 (set frn fpul))
872 (set (dr fsdn) (c-call DF "sh64_fsubd" (dr fsdn) (dr fsdm)))
873 (set fsdn (c-call SF "sh64_fsubs" fsdn fsdm))))
879 (set fpul (if SF prbit
888 (set n (index-of fvn))
889 (set res (c-call SF "sh64_fmuls" (reg h-xf 0) (reg h-frc n)))
890 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 4) (reg h-frc (add n 1)))))
891 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 8) (reg h-frc (add n 2)))))
892 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 12) (reg h-frc (add n 3)))))
893 (set (reg h-frc n) res)
894 (set res (c-call SF "sh64_fmuls" (reg h-xf 1) (reg h-frc n)))
895 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 5) (reg h-frc (add n 1)))))
896 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 9) (reg h-frc (add n 2)))))
897 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 13) (reg h-frc (add n 3)))))
898 (set (reg h-frc (add n 1)) res)
899 (set res (c-call SF "sh64_fmuls" (reg h-xf 2) (reg h-frc n)))
900 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 6) (reg h-frc (add n 1)))))
901 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 10) (reg h-frc (add n 2)))))
902 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 14) (reg h-frc (add n 3)))))
903 (set (reg h-frc (add n 2)) res)
904 (set res (c-call SF "sh64_fmuls" (reg h-xf 3) (reg h-frc n)))
905 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 7) (reg h-frc (add n 1)))))
906 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 11) (reg h-frc (add n 2)))))
907 …(set res (c-call SF "sh64_fadds" res (c-call SF "sh64_fmuls" (reg h-xf 15) (reg h-frc (add n 3)))))
908 (set (reg h-frc (add n 3)) res)))
914 (delay 1 (set pc rn)))
921 (set pr (add pc 4))
922 (set pc rn))))
928 (set gbr rn))
935 (set gbr (mem SI rn))
936 (set rn (add rn 4))))
942 (set fpscr rn))
949 (set fpscr (mem SI rn))
950 (set rn (add rn 4))))
957 (set fpul (subword SF rn 0)))
964 (set fpul (mem SF rn))
965 (set rn (add rn 4))))
971 (set mach rn))
978 (set mach (mem SI rn))
979 (set rn (add rn 4))))
985 (set macl rn))
992 (set macl (mem SI rn))
993 (set rn (add rn 4))))
999 (set pr rn))
1006 (set pr (mem SI rn))
1007 (set rn (add rn 4))))
1014 (set x (mem SI rn))
1015 (set rn (add rn 4))
1018 (set rn (add rn 4))
1019 (set rm (add rm 4))))
1020 (set y (mem SI rm))
1021 (set rm (add rm 4))
1022 (set tmpry (mul (zext DI x) (zext DI y)))
1023 (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
1024 (set result (add mac tmpry))
1028 (set max (srl (inv DI 0) 16))
1030 (set min (srl (inv DI 0) 15))
1032 (set result max)
1034 (set result min)))))
1035 (set mach (subword SI result 0))
1036 (set macl (subword SI result 1)))))
1043 (set x (mem HI rn))
1044 (set rn (add rn 2))
1047 (set rn (add rn 2))
1048 (set rm (add rm 2))))
1049 (set y (mem HI rm))
1050 (set rm (add rm 2))
1051 (set tmpry (mul (zext SI x) (zext SI y)))
1055 (set mach 1))
1056 (set macl (add tmpry macl)))
1058 (set mac (or DI (sll (zext DI mach) 32) (zext DI macl)))
1059 (set result (add mac (ext DI tmpry)))
1060 (set mach (subword SI result 0))
1061 (set macl (subword SI result 1))))))
1067 (set rn64 rm64))
1073 (set rn (ext DI (and QI imm8 255))))
1079 (set (mem UQI rn) (subword UQI rm 3)))
1086 (set addr (sub rn 1))
1087 (set (mem UQI addr) (subword UQI rm 3))
1088 (set rn addr)))
1094 (set (mem UQI (add r0 rn)) (subword UQI rm 3)))
1101 (set addr (add gbr imm8))
1102 (set (mem UQI addr) (subword UQI r0 3))))
1109 (set addr (add rm imm4))
1110 (set (mem UQI addr) (subword UQI r0 3))))
1116 (set rn (ext SI (mem QI rm))))
1123 (set data (mem QI rm))
1125 (set rm (ext SI data))
1126 (set rm (add rm 1)))
1127 (set rn (ext SI data))))
1133 (set rn (ext SI (mem QI (add r0 rm)))))
1139 (set r0 (ext SI (mem QI (add gbr imm8)))))
1145 (set r0 (ext SI (mem QI (add rm imm4)))))
1151 (set (mem SI rn) rm))
1158 (set addr (sub rn 4))
1159 (set (mem SI addr) rm)
1160 (set rn addr)))
1166 (set (mem SI (add r0 rn)) rm))
1172 (set (mem SI (add gbr imm8x4)) r0))
1178 (set (mem SI (add rn imm4x4)) rm))
1184 (set rn (mem SI rm)))
1191 (set rn (mem SI rm))
1193 (set rm rn)
1194 (set rm (add rm 4)))))
1200 (set rn (mem SI (add r0 rm))))
1206 (set r0 (mem SI (add gbr imm8x4))))
1212 (set rn (mem SI (add imm8x4 (and (add pc 4) (inv 3))))))
1218 (set rn (mem SI (add rm imm4x4))))
1224 (set (mem HI rn) (subword HI rm 1)))
1231 (set addr (sub rn 2))
1232 (set (mem HI addr) (subword HI rm 1))
1233 (set rn addr)))
1239 (set (mem HI (add r0 rn)) (subword HI rm 1)))
1245 (set (mem HI (add gbr imm8x2)) (subword HI r0 1)))
1251 (set (mem HI (add rn imm4x2)) (subword HI r0 1)))
1257 (set rn (ext SI (mem HI rm))))
1264 (set data (mem HI rm))
1266 (set rm (ext SI data))
1267 (set rm (add rm 2)))
1268 (set rn (ext SI data))))
1274 (set rn (ext SI (mem HI (add r0 rm)))))
1280 (set r0 (ext SI (mem HI (add gbr imm8x2)))))
1286 (set rn (ext SI (mem HI (add (add pc 4) imm8x2)))))
1292 (set r0 (ext SI (mem HI (add rm imm4x2)))))
1298 (set r0 (add (and (add pc 4) (inv 3)) imm8x4)))
1304 (set (mem SI rn) r0))
1310 (set rn (zext SI tbit)))
1316 (set macl (mul rm rn)))
1322 (set macl (mul (ext SI (subword HI rm 1)) (ext SI (subword HI rn 1)))))
1328 (set macl (mul (zext SI (subword HI rm 1)) (zext SI (subword HI rn 1)))))
1334 (set rn (neg rm)))
1341 (set flag (sub-cflag 0 rm tbit))
1342 (set rn (subc 0 rm tbit))
1343 (set tbit flag)))
1355 (set rn64 (inv rm64)))
1379 (set rn64 (or rm64 rn64)))
1385 (set r0 (or r0 (zext DI uimm8))))
1392 (set addr (add r0 gbr))
1393 (set data (or (mem UQI addr) imm8))
1394 (set (mem UQI addr) data)))
1407 (set temp (srl rn 31))
1408 (set rn (or (sll rn 1) tbit))
1409 (set tbit (if BI temp 1 0))))
1416 (set lsbit (if BI (eq (and rn 1) 0) 0 1))
1417 (set temp tbit)
1418 (set rn (or (srl rn 1) (sll temp 31)))
1419 (set tbit (if BI lsbit 1 0))))
1426 (set temp (srl rn 31))
1427 (set rn (or (sll rn 1) temp))
1428 (set tbit (if BI temp 1 0))))
1435 (set lsbit (if BI (eq (and rn 1) 0) 0 1))
1436 (set temp lsbit)
1437 (set rn (or (srl rn 1) (sll temp 31)))
1438 (set tbit (if BI lsbit 1 0))))
1444 (delay 1 (set pc pr)))
1446 (dshci sets "Set S-bit"
1450 (set sbit 1))
1452 (dshci sett "Set T-bit"
1456 (set tbit 1))
1463 (set shamt (and QI rm 31))
1465 (set rn (sll rn shamt))
1467 (set rn (sra rn (sub 32 shamt)))
1469 (set rn (neg 1))
1470 (set rn 0))))))
1477 (set t (srl rn 31))
1478 (set rn (sll rn 1))
1479 (set tbit (if BI t 1 0))))
1486 (set t (and rn 1))
1487 (set rn (sra rn 1))
1488 (set tbit (if BI t 1 0))))
1495 (set shamt (and QI rm 31))
1497 (set rn (sll rn shamt))
1499 (set rn (srl rn (sub 32 shamt)))
1500 (set rn 0)))))
1507 (set t (srl rn 31))
1508 (set rn (sll rn 1))
1509 (set tbit (if BI t 1 0))))
1515 (set rn (sll rn 2)))
1521 (set rn (sll rn 8)))
1527 (set rn (sll rn 16)))
1534 (set t (and rn 1))
1535 (set rn (srl rn 1))
1536 (set tbit (if BI t 1 0))))
1542 (set rn (srl rn 2)))
1548 (set rn (srl rn 8)))
1554 (set rn (srl rn 16)))
1560 (set rn gbr))
1567 (set addr (sub rn 4))
1568 (set (mem SI addr) gbr)
1569 (set rn addr)))
1575 (set rn fpscr))
1582 (set addr (sub rn 4))
1583 (set (mem SI addr) fpscr)
1584 (set rn addr)))
1590 (set rn (subword SI fpul 0)))
1597 (set addr (sub rn 4))
1598 (set (mem SF addr) fpul)
1599 (set rn addr)))
1605 (set rn mach))
1612 (set addr (sub rn 4))
1613 (set (mem SI addr) mach)
1614 (set rn addr)))
1620 (set rn macl))
1627 (set addr (sub rn 4))
1628 (set (mem SI addr) macl)
1629 (set rn addr)))
1635 (set rn pr))
1642 (set addr (sub rn 4))
1643 (set (mem SI addr) pr)
1644 (set rn addr)))
1650 (set rn (sub rn rm)))
1657 (set flag (sub-cflag rn rm tbit))
1658 (set rn (subc rn rm tbit))
1659 (set tbit flag)))
1666 (set t (sub-oflag rn rm 0))
1667 (set rn (sub rn rm))
1668 (set tbit (if BI t 1 0))))
1675 (set top-half (subword HI rm 0))
1676 (set byte1 (subword QI rm 2))
1677 (set byte0 (subword QI rm 3))
1678 (set rn (or SI (sll SI top-half 16) (or SI (sll SI byte0 8) byte1)))))
1684 (set rn (or (srl rm 16) (sll rm 16))))
1686 (dshci tasb "Test and set byte"
1691 (set byte (mem UQI rn))
1692 (set tbit (if BI (eq byte 0) 1 0))
1693 (set byte (or byte 128))
1694 (set (mem UQI rn) byte)))
1702 (dshci tst "Test and set t-bit"
1706 (set tbit (if BI (eq (and rm rn) 0) 1 0)))
1708 (dshci tsti "Test and set t-bit immediate"
1712 (set tbit (if BI (eq (and r0 (zext SI uimm8)) 0) 1 0)))
1714 (dshci tstb "Test and set t-bit immedate with memory byte"
1719 (set addr (add r0 gbr))
1720 (set tbit (if BI (eq (and (mem UQI addr) imm8) 0) 1 0))))
1726 (set rn64 (xor rn64 rm64)))
1732 (set (reg h-gr 0) (xor (reg h-gr 0) (zext DI uimm8))))
1739 (set addr (add r0 gbr))
1740 (set data (xor (mem UQI addr) imm8))
1741 (set (mem UQI addr) data)))
1747 (set rn (or (sll rm 16) (srl rn 16))))