Lines Matching +full:fine +full:- +full:tuning
1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
123 // Expand general-regs-only to -x86, -mmx and -sse in initFeatureMap()
124 if (Feature == "+general-regs-only") { in initFeatureMap()
125 UpdatedFeaturesVec.push_back("-x87"); in initFeatureMap()
126 UpdatedFeaturesVec.push_back("-mmx"); in initFeatureMap()
127 UpdatedFeaturesVec.push_back("-sse"); in initFeatureMap()
142 if (I != Features.end() && I->getValue() && in initFeatureMap()
143 !llvm::is_contained(UpdatedFeaturesVec, "-popcnt")) in initFeatureMap()
149 if (I != Features.end() && I->getValue() && in initFeatureMap()
150 !llvm::is_contained(UpdatedFeaturesVec, "-mmx")) in initFeatureMap()
155 if (I != Features.end() && I->getValue() && in initFeatureMap()
156 !llvm::is_contained(UpdatedFeaturesVec, "-xsave")) in initFeatureMap()
161 if (I != Features.end() && I->getValue() && in initFeatureMap()
162 !llvm::is_contained(UpdatedFeaturesVec, "-crc32")) in initFeatureMap()
172 // via the -msse4/-mno-sse4 command line alias. Handle this the same way in setFeatureEnabled()
173 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if in setFeatureEnabled()
185 /// handleTargetFeatures - Perform initialization based on the user
310 } else if (Feature == "+retpoline-external-thunk") { in handleTargetFeatures()
326 } else if (Feature == "+save-args") { in handleTargetFeatures()
332 } else if (Feature == "+amx-bf16") { in handleTargetFeatures()
334 } else if (Feature == "+amx-fp16") { in handleTargetFeatures()
336 } else if (Feature == "+amx-int8") { in handleTargetFeatures()
338 } else if (Feature == "+amx-tile") { in handleTargetFeatures()
408 // FIXME: We should allow long double type on 32-bits to match with GCC. in handleTargetFeatures()
416 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
448 // FIXME: We are hard-coding the tune parameters based on the CPU, but they in getTargetDefines()
449 // truly should be based on -mtune options. in getTargetDefines()
537 // remove it at some point. We've never exposed fine-grained names for in getTargetDefines()
547 defineCPUMacros(Builder, "i586", /*Tuning*/false); in getTargetDefines()
548 defineCPUMacros(Builder, "pentium", /*Tuning*/false); in getTargetDefines()
558 // architecture is specified but -m3dnow is explicitly provided. The in getTargetDefines()
642 // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM, in getTargetDefines()
643 // the feature flag only applies to 64-bit mode. in getTargetDefines()
853 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. in getTargetDefines()
857 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. in getTargetDefines()
919 .Case("amx-bf16", true) in isValidFeatureName()
920 .Case("amx-fp16", true) in isValidFeatureName()
921 .Case("amx-int8", true) in isValidFeatureName()
922 .Case("amx-tile", true) in isValidFeatureName()
960 .Case("general-regs-only", true) in isValidFeatureName()
1020 .Case("amx-bf16", HasAMXBF16) in hasFeature()
1021 .Case("amx-fp16", HasAMXFP16) in hasFeature()
1022 .Case("amx-int8", HasAMXINT8) in hasFeature()
1023 .Case("amx-tile", HasAMXTILE) in hasFeature()
1075 .Case("save-args", HasSaveArgs) in hasFeature()
1090 .Case("retpoline-external-thunk", HasRetpolineExternalThunk) in hasFeature()
1190 WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false); in getCPUSpecificCPUDispatchFeatures()
1256 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 in validateAsmConstraint()
1258 case 'Z': // 32-bit unsigned integer constant for use with zero-extending in validateAsmConstraint()
1270 Info.setRequiresImmediate(-128, 127); in validateAsmConstraint()
1285 case 'Y': // 'Y' is the first character for several 2-character constraints. in validateAsmConstraint()
1294 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. in validateAsmConstraint()
1295 case 'm': // Any MMX register, when inter-unit moves enabled. in validateAsmConstraint()
1296 case 'k': // AVX512 arch mask registers: k1-k7. in validateAsmConstraint()
1334 Name += Len - 1; in validateAsmConstraint()
1343 …------------------------------------+-------------------------+-----------------------------------…
1345 …------------------------------------+-------------------------+-----------------------------------…
1346 …intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manua…
1348 // | i586/Pentium MMX | 32 | https://www.7-cpu.com/cpu/P-MMX…
1349 // | i686/Pentium | 32 | https://www.7-cpu.com/cpu/P6.ht…
1350 // | Netburst/Pentium4 | 64 | https://www.7-cpu.com/cpu/P4-18…
1351 // | Atom | 64 | https://www.7-cpu.com/cpu/Atom.…
1353 … 64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBrid…
1354 … 64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu…
1355 // | Haswell | 64 | https://www.7-cpu.com/cpu/Haswe…
1356 // | Boadwell | 64 | https://www.7-cpu.com/cpu/Broad…
1357 // | Skylake (including skylake-avx512) | 64 | https://www.nas.nasa.gov/hecc/s…
1358 … 64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html…
1360 // | Ice Lake | 64 | https://www.7-cpu.com/cpu/Ice_L…
1361 … 64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory…
1362 …s://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manua…
1363 …------------------------------------+-------------------------+-----------------------------------…
1494 // Registers k0-k7 (AVX512) size limit is 64 bit. in validateOperandSize()
1502 // 'Y' is the first character for several 2-character constraints. in validateOperandSize()
1533 // 512-bit zmm registers can be used if target supports AVX512F. in validateOperandSize()
1536 // 256-bit ymm registers can be used if target supports AVX. in validateOperandSize()
1550 Constraint += Len - 1; in convertConstraint()
1614 return llvm::ArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - in getTargetBuiltins()
1620 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); in getTargetBuiltins()