Lines Matching refs:uint16_t
57 uint16_t smbh_hdl; /* structure handle */
64 uint16_t smbbi_segment; /* segment location of bios address */
92 uint16_t smbbb_chassis; /* chassis handle */
95 uint16_t smbbb_cv[1]; /* array of contained handles */
128 uint16_t smbpr_clkspeed; /* external clock speed in MHz */
129 uint16_t smbpr_maxspeed; /* maximum speed in MHz */
130 uint16_t smbpr_curspeed; /* current speed in MHz */
133 uint16_t smbpr_l1cache; /* L1 cache handle (if any) */
134 uint16_t smbpr_l2cache; /* L2 cache handle (if any) */
135 uint16_t smbpr_l3cache; /* L3 cache handle (if any) */
144 uint16_t smbca_config; /* cache configuration */
145 uint16_t smbca_maxsize; /* maximum installed size */
146 uint16_t smbca_size; /* installed size */
147 uint16_t smbca_stype; /* supported SRAM type */
148 uint16_t smbca_ctype; /* current SRAM type */
185 uint16_t smbsl_id; /* slot ID */
188 uint16_t smbsl_sg; /* segment group number */
215 uint16_t smbsel_len; /* log area length */
216 uint16_t smbsel_hdroff; /* header offset */
217 uint16_t smbsel_dataoff; /* data offset */
234 uint16_t smbmarr_err; /* error handle */
235 uint16_t smbmarr_ndevs; /* number of slots or sockets */
242 uint16_t smbamap_array; /* physical memory array handle */
248 uint16_t smbmdev_array; /* array handle */
249 uint16_t smbmdev_error; /* error handle */
250 uint16_t smbmdev_twidth; /* total width */
251 uint16_t smbmdev_dwidth; /* data width */
252 uint16_t smbmdev_size; /* size in either K or MB */
258 uint16_t smbmdev_flags; /* detail flags */
259 uint16_t smbmdev_speed; /* speed in MHz */
272 uint16_t smbdmap_device; /* memory device handle */
273 uint16_t smbdmap_array; /* memory array mapped address handle */
287 uint16_t smbbat_cap; /* design capacity in mW hours */
288 uint16_t smbbat_volt; /* design voltage in mV */
291 uint16_t smbbat_ssn; /* SBDS serial number */
292 uint16_t smbbat_sdate; /* SBDS manufacture date */
356 uint16_t smbpsup_max; /* max output in milliwatts */
357 uint16_t smbpsup_char; /* characteristics */
358 uint16_t smbpsup_vprobe; /* voltage probe handle */
359 uint16_t smbpsup_cooldev; /* cooling device handle */
360 uint16_t smbpsup_iprobe; /* current probe handle */
368 uint16_t smbobe_sg; /* segment group number */
375 uint16_t smbpre_processor; /* processor handle */
378 uint16_t smbpre_apicid[1]; /* strand initial apic id */
383 uint16_t smbpoe_chassis; /* chassis handle */
384 uint16_t smbpoe_port; /* port connector handle */
386 uint16_t smbpoe_devhdl; /* device handle */
392 uint16_t smbpciexrc_bboard; /* base board handle */
393 uint16_t smbpciexrc_bdf; /* PCI Bus/Dev/Func */
398 uint16_t smbmarre_ma; /* memory array handle */
399 uint16_t smbmarre_component; /* component parent handle */
400 uint16_t smbmarre_bdf; /* PCI bus/dev/funct */
405 uint16_t smbmdeve_mdev; /* memory device handle */
418 uint16_t *smbst_strtab; /* string index -> offset table */