Lines Matching defs:trb
530 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
533 trb->trb_0 = htole64(parameter);
534 trb->trb_2 = htole32(status);
535 trb->trb_3 = htole32(control);
1860 struct xhci_soft_trb trb;
1880 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
1881 trb.trb_2 = 0;
1882 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1885 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
1916 struct xhci_soft_trb trb;
1923 trb.trb_0 = 0;
1924 trb.trb_2 = 0;
1925 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1929 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) {
1944 struct xhci_soft_trb trb;
1952 trb.trb_0 = 0;
1953 trb.trb_2 = 0;
1954 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
1959 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
1994 struct xhci_soft_trb trb;
2005 trb.trb_0 = xhci_ring_trbp(xr, 0) | 1; /* XXX */
2006 trb.trb_2 = 0;
2007 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2011 if (xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT)) {
2118 struct xhci_soft_trb trb;
2171 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
2172 trb.trb_2 = 0;
2173 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
2176 (void)xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
2380 const struct xhci_trb * const trb)
2394 trb_0 = le64toh(trb->trb_0);
2395 trb_2 = le32toh(trb->trb_2);
2396 trb_3 = le32toh(trb->trb_3);
2561 xhci_event_cmd(struct xhci_softc * const sc, const struct xhci_trb * const trb)
2570 trb_0 = le64toh(trb->trb_0);
2571 trb_2 = le32toh(trb->trb_2);
2572 trb_3 = le32toh(trb->trb_3);
2589 "0x%08jx 0x%08jx", (uintptr_t)trb, trb_0, trb_2, trb_3);
2599 const struct xhci_trb * const trb)
2606 trb_0 = le64toh(trb->trb_0);
2607 trb_2 = le32toh(trb->trb_2);
2608 trb_3 = le32toh(trb->trb_3);
2611 (uintptr_t)trb, trb_0, trb_2, trb_3);
2631 xhci_event_transfer(sc, trb);
2634 xhci_event_cmd(sc, trb);
2650 struct xhci_trb *trb;
2679 trb = &er->xr_trb[i];
2680 k = (le32toh(trb->trb_3) & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
2685 xhci_handle_event(sc, trb);
3097 * that a LINK trb is only allowed at the end of a burst of
3099 * Arbitrary aligned LINK trb definitely fail on Ivy bridge.
3100 * The simple solution is not to allow a LINK trb in the middle
3103 * ASMedia) that seem to lock up if they process a LINK trb but
3104 * cannot process the linked-to trb yet.
3105 * The code should write the 'cycle' bit on the link trb AFTER
3106 * adding the other trb.
3230 struct xhci_soft_trb * const trb, int timeout)
3237 trb->trb_0, trb->trb_2, trb->trb_3, 0);
3260 xhci_ring_put(sc, cr, NULL, trb, 1);
3274 trb->trb_0 = sc->sc_result_trb.trb_0;
3275 trb->trb_2 = sc->sc_result_trb.trb_2;
3276 trb->trb_3 = sc->sc_result_trb.trb_3;
3279 trb->trb_0, trb->trb_2, trb->trb_3, 0);
3281 switch (XHCI_TRB_2_ERROR_GET(trb->trb_2)) {
3288 XHCI_TRB_2_ERROR_GET(trb->trb_2), 0, 0, 0);
3305 xhci_do_command(struct xhci_softc * const sc, struct xhci_soft_trb * const trb,
3310 usbd_status ret = xhci_do_command_locked(sc, trb, timeout);
3319 struct xhci_soft_trb trb;
3324 trb.trb_0 = 0;
3325 trb.trb_2 = 0;
3326 trb.trb_3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT);
3328 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
3333 *slotp = XHCI_TRB_3_SLOT_GET(trb.trb_3);
3347 struct xhci_soft_trb trb;
3356 trb.trb_0 = 0;
3357 trb.trb_2 = 0;
3358 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot) |
3361 err = xhci_do_command_locked(sc, &trb, USBD_DEFAULT_TIMEOUT);
3386 struct xhci_soft_trb trb;
3398 trb.trb_0 = icp;
3399 trb.trb_2 = 0;
3400 trb.trb_3 = XHCI_TRB_3_SLOT_SET(slot_id) |
3404 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);
3406 if (XHCI_TRB_2_ERROR_GET(trb.trb_2) == XHCI_TRB_ERROR_NO_SLOTS)
3416 struct xhci_soft_trb trb;
3435 trb.trb_0 = xhci_slot_get_icp(sc, xs, 0);
3436 trb.trb_2 = 0;
3437 trb.trb_3 = XHCI_TRB_3_SLOT_SET(xs->xs_idx) |
3440 err = xhci_do_command(sc, &trb, USBD_DEFAULT_TIMEOUT);