Lines Matching +defs:parameter +defs:value
307 uint32_t value)
309 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, value);
315 uint32_t value)
317 bus_space_write_4(sc->sc_iot, sc->sc_ioh, offset, value);
335 uint32_t value)
337 bus_space_write_4(sc->sc_iot, sc->sc_obh, offset, value);
343 uint64_t value;
346 value = bus_space_read_8(sc->sc_iot, sc->sc_obh, offset);
348 value = bus_space_read_4(sc->sc_iot, sc->sc_obh, offset);
349 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_obh,
353 return value;
358 uint64_t value)
361 bus_space_write_8(sc->sc_iot, sc->sc_obh, offset, value);
364 (value >> 0) & 0xffffffff);
366 (value >> 32) & 0xffffffff);
378 uint32_t value)
380 bus_space_write_4(sc->sc_iot, sc->sc_rbh, offset, value);
386 uint64_t value;
389 value = bus_space_read_8(sc->sc_iot, sc->sc_rbh, offset);
391 value = bus_space_read_4(sc->sc_iot, sc->sc_rbh, offset);
392 value |= (uint64_t)bus_space_read_4(sc->sc_iot, sc->sc_rbh,
396 return value;
401 uint64_t value)
404 bus_space_write_8(sc->sc_iot, sc->sc_rbh, offset, value);
407 (value >> 0) & 0xffffffff);
409 (value >> 32) & 0xffffffff);
423 uint32_t value)
425 bus_space_write_4(sc->sc_iot, sc->sc_dbh, offset, value);
521 uint64_t parameter, uint32_t status, uint32_t control)
524 xx->xx_trb[idx].trb_0 = parameter;
530 xhci_trb_put(struct xhci_trb * const trb, uint64_t parameter, uint32_t status,
533 trb->trb_0 = htole64(parameter);
998 * `7. Write the CRCR with the address and RCS value of the
1797 * Speed value is always 0 for Super Speed or more, and dwExtPortStatus
3072 uint64_t parameter;
3117 parameter = xhci_ring_trbp(xr, 0);
3127 parameter = trbs[i].trb_0;
3152 xhci_trb_put(&xr->xr_trb[oldri], parameter, status, control);
3977 * Convert usbdi bInterval value to xhci endpoint context interval value
4041 uint16_t len, value, index;
4055 value = UGETW(req->wValue);
4059 req->bmRequestType | (req->bRequest << 8), value, index, len);
4064 DPRINTFN(8, "getdesc: wValue=0x%04jx", value, 0, 0, 0);
4067 switch (value) {
4088 index, value, bn, cp);
4096 switch (value) {
4134 if ((value & 0xff) != 0) {
4231 switch (value) {
4429 uint64_t parameter;
4453 parameter = le64dec(req); /* to keep USB endian after xhci_trb_put() */
4459 xhci_xfer_put_trb(xx, i++, parameter, status, control);
4463 parameter = DMAADDR(dma, 0);
4472 xhci_xfer_put_trb(xx, i++, parameter, status, control);
4478 parameter = 0;
4484 xhci_xfer_put_trb(xx, i++, parameter, status, control);
4558 uint64_t parameter;
4610 parameter = DMAADDR(dma, offs);
4632 xhci_xfer_put_trb(xx, i, parameter, status, control);
4708 uint64_t parameter;
4728 parameter = DMAADDR(dma, 0);
4752 xhci_xfer_put_trb(xx, i++, parameter, status, control);
4832 uint64_t parameter;
4856 parameter = DMAADDR(dma, 0);
4863 xhci_xfer_put_trb(xx, i++, parameter, status, control);