Lines Matching defs:dci
479 const u_int dci)
481 return KERNADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
487 const u_int dci)
489 return DMAADDR(&xs->xs_dc_dma, sc->sc_ctxsz * dci);
556 u_int dci)
561 cp = xhci_slot_get_dcv(sc, xs, dci);
689 size_t i, j, bn, dci;
738 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
741 if (xhci_get_epstate(sc, xs, dci) !=
747 err = xhci_stop_endpoint_cmd(sc, xs, dci,
752 " slot %zu dci %zu err %d\n",
753 i, dci, err);
915 size_t i, j, bn, dci;
1093 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
1095 if (xhci_get_epstate(sc, xs, dci) !=
1100 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
1858 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1864 XHCIHIST_CALLARGS("slot %ju dci %ju epaddr 0x%02jx attr 0x%02jx",
1865 xs->xs_idx, dci, pipe->up_endpoint->ue_edesc->bEndpointAddress,
1878 xhci_dci_to_ici(dci)), sc->sc_ctxsz * 1);
1888 HEXDUMP("output context", xhci_slot_get_dcv(sc, xs, dci),
1915 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1919 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1926 XHCI_TRB_3_EP_SET(dci) |
1941 xhci_stop_endpoint_cmd(struct xhci_softc *sc, struct xhci_slot *xs, u_int dci,
1948 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1955 XHCI_TRB_3_EP_SET(dci) |
1969 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1972 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
1976 return xhci_stop_endpoint_cmd(sc, xs, dci, 0);
1992 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
1993 struct xhci_ring * const xr = xs->xs_xr[dci];
1997 XHCIHIST_CALLARGS("slot %ju dci %ju", xs->xs_idx, dci, 0, 0);
2008 XHCI_TRB_3_EP_SET(dci) |
2030 const u_int dci = xhci_ep_get_dci(ed);
2037 DPRINTFN(1, " dci %ju type 0x%02jx epaddr 0x%02jx attr 0x%02jx",
2088 KASSERT(xs->xs_xr[dci] == NULL);
2091 err = xhci_ring_init(sc, &xs->xs_xr[dci], XHCI_TRANSFER_RING_TRBS,
2117 const u_int dci = xhci_ep_get_dci(ed);
2133 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju",
2134 (uintptr_t)pipe, xs->xs_idx, dci, 0);
2142 if (dci == XHCI_DCI_EP_CONTROL) {
2149 if (xhci_get_epstate(sc, xs, dci) != XHCI_EPSTATE_STOPPED)
2158 cp[0] = htole32(XHCI_INCTX_0_DROP_MASK(dci));
2161 /* XXX should be most significant one, not dci? */
2163 cp[0] = htole32(XHCI_SCTX_0_CTX_NUM_SET(dci));
2166 xhci_host_dequeue(xs->xs_xr[dci]);
2179 xhci_ring_free(sc, &xs->xs_xr[dci]);
2180 xs->xs_xr[dci] = NULL;
2230 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2233 XHCIHIST_CALLARGS("pipe %#jx slot %ju dci %ju",
2234 (uintptr_t)pipe, xs->xs_idx, dci, 0);
2246 switch (xhci_get_epstate(sc, xs, dci)) {
2257 switch (xhci_get_epstate(sc, xs, dci)) {
2280 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2281 struct xhci_ring * const tr = xs->xs_xr[dci];
2329 const u_int dci = xhci_ep_get_dci(pipe->up_endpoint->ue_edesc);
2330 struct xhci_ring * const tr = xs->xs_xr[dci];
2385 u_int slot, dci;
2399 dci = XHCI_TRB_3_EP_GET(trb_3);
2401 xr = xs->xs_xr[dci];
2424 DPRINTFN(1, "Ignore #%ju: cookie %#jx cc %ju dci %ju",
2425 idx, (uintptr_t)xx, trbcode, dci);
2517 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
2522 DPRINTFN(1, "ERR %ju slot %ju dci %ju", trbcode, slot, dci, 0);
3504 u_int dci;
3510 for (dci = XHCI_DCI_SLOT; dci <= XHCI_MAX_DCI; dci++) {
3511 if (xs->xs_xr[dci] != NULL)
3512 xhci_ring_free(sc, &xs->xs_xr[dci]);
3562 const u_int dci = xhci_ep_get_dci(ed);
3568 XHCIHIST_CALLARGS("pipe %#jx: slot %ju dci %ju speed %ju",
3569 (uintptr_t)pipe, xs->xs_idx, dci, speed);
3574 cp[1] = htole32(XHCI_INCTX_1_ADD_MASK(dci));
3581 XHCI_SCTX_0_CTX_NUM_SET(dci) |
3595 cp = xhci_slot_get_icv(sc, xs, xhci_dci_to_ici(dci));
3612 DPRINTFN(4, "setting on dci %ju ival %ju mult %ju mps %#jx",
3613 dci, XHCI_EPCTX_0_IVAL_GET(cp[0]), XHCI_EPCTX_0_MULT_GET(cp[0]),
3624 xhci_ring_trbp(xs->xs_xr[dci], 0) |
3632 struct xhci_ring *xr = xs->xs_xr[dci];
4422 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4423 struct xhci_ring * const tr = xs->xs_xr[dci];
4492 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4553 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4554 struct xhci_ring * const tr = xs->xs_xr[dci];
4569 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4570 (uintptr_t)xfer, xs->xs_idx, dci, 0);
4646 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4674 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4679 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4680 (uintptr_t)xfer, xs->xs_idx, dci, 0);
4703 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4704 struct xhci_ring * const tr = xs->xs_xr[dci];
4715 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4716 (uintptr_t)xfer, xs->xs_idx, dci, 0);
4760 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4781 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4786 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4787 (uintptr_t)xfer, xs->xs_idx, dci, 0);
4826 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4827 struct xhci_ring * const tr = xs->xs_xr[dci];
4838 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4839 (uintptr_t)xfer, xs->xs_idx, dci, 0);
4871 xhci_db_write_4(sc, XHCI_DOORBELL(xs->xs_idx), dci);
4893 const u_int dci = xhci_ep_get_dci(xfer->ux_pipe->up_endpoint->ue_edesc);
4898 XHCIHIST_CALLARGS("%#jx slot %ju dci %ju",
4899 (uintptr_t)xfer, xs->xs_idx, dci, 0);