Lines Matching defs:resp
120 #define MMC_R1(resp) ((resp)[0])
121 #define MMC_R3(resp) ((resp)[0])
122 #define SD_R6(resp) ((resp)[0])
123 #define MMC_R7(resp) ((resp)[0])
124 #define MMC_SPI_R1(resp) ((resp)[0])
125 #define MMC_SPI_R7(resp) ((resp)[1])
129 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
220 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
225 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
231 #define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
232 #define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4)
233 #define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3)
234 #define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
235 #define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
236 #define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
237 #define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
238 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
239 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
240 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
241 (MMC_CSD_C_SIZE_MULT((resp))+2))
242 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
243 #define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
244 #define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
247 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
248 #define MMC_CID_PNM_V1_CPY(resp, pnm) \
250 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
251 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
252 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
253 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
254 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
255 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
256 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
259 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
260 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
261 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
264 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
265 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
266 #define MMC_CID_PNM_V2_CPY(resp, pnm) \
268 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
269 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
270 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
271 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
272 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
273 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
276 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
279 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
282 #define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
283 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
284 #define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4)
285 #define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3)
287 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
288 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
289 #define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4)
290 #define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3)
293 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
303 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
304 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
305 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
306 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
307 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
308 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
309 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
310 (SD_CSD_C_SIZE_MULT((resp))+2))
311 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
312 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
313 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
314 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
317 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
318 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
320 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
321 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
322 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
323 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
324 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
325 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
326 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
329 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
330 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
331 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
332 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
333 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
334 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
337 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
338 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
339 #define SD_CID_PNM_CPY(resp, pnm) \
341 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
342 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
343 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
344 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
345 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
348 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
349 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
350 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
377 #define SSR_DAT_BUS_WIDTH(resp) __bitfield((resp), 510, 2)
380 #define SSR_SECURED_MODE(resp) __bitfield((resp), 509, 1)
381 #define SSR_SD_CARD_TYPE(resp) __bitfield((resp), 480, 16)
385 #define SSR_SIZE_OF_PROTECTED_AREA(resp) __bitfield((resp), 448, 32)
386 #define SSR_SPEED_CLASS(resp) __bitfield((resp), 440, 8)
392 #define SSR_PERFORMANCE_MOVE(resp) __bitfield((resp), 432, 8)
393 #define SSR_AU_SIZE(resp) __bitfield((resp), 428, 4)
394 #define SSR_ERASE_SIZE(resp) __bitfield((resp), 408, 16)
395 #define SSR_ERASE_TIMEOUT(resp) __bitfield((resp), 402, 6)
396 #define SSR_ERASE_OFFSET(resp) __bitfield((resp), 400, 2)
397 #define SSR_UHS_SPEED_GRADE(resp) __bitfield((resp), 396, 4)
400 #define SSR_UHS_AU_SIZE(resp) __bitfield((resp), 392, 4)
401 #define SSR_VIDEO_SPEED_CLASS(resp) __bitfield((resp), 384, 8)
402 #define SSR_VSC_AU_SIZE(resp) __bitfield((resp), 368, 10)
403 #define SSR_SUS_ADDR(resp) __bitfield((resp), 346, 22)
404 #define SSR_APP_PERF_CLASS(resp) __bitfield((resp), 336, 4)
408 #define SSR_PERFORMANCE_ENHANCE(resp) __bitfield((resp), 328, 8)
413 #define SSR_DISCARD_SUPPORT(resp) __bitfield((resp), 313, 1)
414 #define SSR_FULE_SUPPORT(resp) __bitfield((resp), 312, 1)
450 #define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start)-8, (len))