Lines Matching defs:phyreg
13257 uint16_t id1, id2, phyreg;
13276 sc->phy.readreg_locked(sc->sc_dev, i, MAKPHY_ESSR, &phyreg);
13277 phyreg &= ~(ESSR_SER_ANEG_BYPASS | ESSR_HWCFG_MODE);
13278 phyreg |= ESSR_SGMII_WOC_COPPER;
13279 sc->phy.writereg_locked(sc->sc_dev, i, MAKPHY_ESSR, phyreg);
16392 uint16_t phyreg;
16440 rv = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, CV_SMB_CTRL, &phyreg);
16452 &phyreg);
16456 phyreg &= ~CV_SMB_CTRL_FORCE_SMBUS;
16457 wm_gmii_hv_writereg_locked(sc->sc_dev, 2, CV_SMB_CTRL, phyreg);
16464 rv = wm_gmii_hv_readreg_locked(sc->sc_dev, 2, HV_PM_CTRL, &phyreg);
16467 phyreg |= HV_PM_CTRL_K1_ENA;
16468 wm_gmii_hv_writereg_locked(sc->sc_dev, 2, HV_PM_CTRL, phyreg);
16471 &phyreg);
16474 phyreg &= ~(I218_ULP_CONFIG1_IND
16482 wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, phyreg);
16483 phyreg |= I218_ULP_CONFIG1_START;
16484 wm_gmii_hv_writereg_locked(sc->sc_dev, 2, I218_ULP_CONFIG1, phyreg);
16588 uint16_t phyreg;
16605 sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL, &phyreg);
16606 phyreg &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
16607 phyreg |= IGP3_VR_CTRL_MODE_SHUTDOWN;
16608 sc->sc_mii.mii_writereg(sc->sc_dev, 1, IGP3_VR_CTRL, phyreg);
16611 sc->sc_mii.mii_readreg(sc->sc_dev, 1, IGP3_VR_CTRL, &phyreg);
16612 phyreg &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
16613 if ((phyreg == IGP3_VR_CTRL_MODE_SHUTDOWN) || (i != 0))
17146 uint16_t phyreg;
17161 rv = mii->mii_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG, &phyreg);
17164 rv = mii->mii_readreg(sc->sc_dev, 1, IGP3_KMRN_DIAG, &phyreg);
17168 if ((phyreg & IGP3_KMRN_DIAG_PCS_LOCK_LOSS) == 0)
17596 uint16_t phyreg;
17605 &phyreg);
17609 phyreg & ~KUMCTRLSTA_K1_ENABLE);
17616 &phyreg);
17630 wm_gmii_hv_readreg(sc->sc_dev, 2, I217_INBAND_CTRL, &phyreg);
17633 phyreg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
17636 phyreg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
17642 phyreg |= 50 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
17648 wm_gmii_hv_writereg(sc->sc_dev, 2, I217_INBAND_CTRL, phyreg);
17707 uint16_t phyreg;
17714 rv = wm_gmii_hv_readreg(sc->sc_dev, 2, HV_M_STATUS, &phyreg);
17718 if ((phyreg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
17720 if (phyreg &
17724 &phyreg);
17727 phyreg &= ~HV_PM_CTRL_K1_ENA;
17729 phyreg);
17758 uint16_t phyreg;
17764 wm_gmii_hv_readreg(sc->sc_dev, 2, MII_BMCR, &phyreg);
17765 if ((phyreg & BMCR_LOOP) != 0)
17769 wm_gmii_hv_readreg(sc->sc_dev, 2, BM_CS_STATUS, &phyreg);
17770 phyreg &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED
17772 if (phyreg != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED
17978 uint16_t phyreg;
17982 CV_SMB_CTRL, &phyreg);
17983 phyreg &= ~CV_SMB_CTRL_FORCE_SMBUS;
17985 CV_SMB_CTRL, phyreg);