Lines Matching defs:phy_reg
10583 uint16_t phy_reg;
10586 I217_PLL_CLOCK_GATE_REG, &phy_reg);
10587 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
10590 phy_reg |= 0x3e8;
10592 phy_reg |= 0xfa;
10594 I217_PLL_CLOCK_GATE_REG, phy_reg);
10598 HV_PM_CTRL, &phy_reg);
10600 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
10603 HV_PM_CTRL, phy_reg);
12577 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
12579 * Assumes semaphore already acquired and phy_reg points to a valid memory
12630 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
12634 * Assumes semaphore already acquired and *phy_reg is the contents of the
16679 uint16_t anar, phy_reg;
16689 I217_LPI_GPIO_CTRL, &phy_reg);
16690 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
16692 I217_LPI_GPIO_CTRL, phy_reg);
16763 uint16_t phy_reg;
16770 sc->phy.readreg_locked(dev, 1, I217_LPI_GPIO_CTRL, &phy_reg);
16771 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
16772 sc->phy.writereg_locked(dev, 1, I217_LPI_GPIO_CTRL, phy_reg);
16779 &phy_reg);
16782 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
16783 sc->phy.writereg_locked(dev, 1, I217_MEMPWR, phy_reg);
16789 sc->phy.readreg_locked(dev, 1, I217_CFGREG, &phy_reg);
16792 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
16793 sc->phy.writereg_locked(dev, 1, I217_CFGREG, phy_reg);