Lines Matching defs:CSR_READ
791 #define CSR_READ(sc, reg) \
796 (void)CSR_READ((sc), WMREG_STATUS)
1874 if (CSR_READ(sc, reg) & SCTL_CTL_READY)
2303 sc->sc_funcid = (CSR_READ(sc, WMREG_STATUS)
2349 reg = CSR_READ(sc, WMREG_STATUS);
2423 CSR_READ(sc, WMREG_COLC);
2424 CSR_READ(sc, WMREG_RXERRC);
2450 reg = CSR_READ(sc, WMREG_EECD);
2466 reg = CSR_READ(sc, WMREG_EECD);
2592 (((CSR_READ(sc, WMREG_STRAP) >> 1) & 0x1F) + 1)
2631 reg = CSR_READ(sc, WMREG_SWSM2);
2648 reg = CSR_READ(sc, WMREG_SWSM);
2714 eeprom_data = CSR_READ(sc, WMREG_WUC);
3020 reg = CSR_READ(sc, WMREG_CTRL_EXT);
3090 (CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
3767 reg = CSR_READ(sc, WMREG_WUS);
4338 wlock_mac = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM),
4492 i = __SHIFTOUT(CSR_READ(sc, WMREG_FWSM), FWSM_WLOCK_MAC);
4559 hash = CSR_READ(sc, mta_reg + (reg << 2));
4568 bit = CSR_READ(sc, mta_reg + ((reg - 1) << 2));
4628 gcr = CSR_READ(sc, WMREG_GCR);
4675 if (CSR_READ(sc, WMREG_EECD) & EECD_EE_AUTORD)
4708 reg = CSR_READ(sc, WMREG_STATUS);
4777 if (CSR_READ(sc, WMREG_EEMNGCTL) & mask)
4801 reg = CSR_READ(sc, WMREG_STATUS);
4856 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
4882 KASSERT(CSR_READ(sc, WMREG_EXTCNFCTR) & EXTCNFCTR_MDIO_SW_OWNERSHIP);
4884 strap = CSR_READ(sc, WMREG_STRAP);
4951 reg = CSR_READ(sc, WMREG_FEXTNVM);
4959 extcnfctr = CSR_READ(sc, WMREG_EXTCNFCTR);
4969 reg = CSR_READ(sc, WMREG_EXTCNFSIZE);
4988 reg = CSR_READ(sc, WMREG_LEDCTL);
5045 mac_reg = CSR_READ(sc, WMREG_EXTCNFCTR);
5050 mac_reg = CSR_READ(sc, WMREG_FEXTNVM);
5054 mac_reg = CSR_READ(sc, WMREG_PHY_CTRL);
5102 reg = CSR_READ(sc, WMREG_TXDCTL(0));
5107 reg = CSR_READ(sc, WMREG_TXDCTL(1));
5112 tarc0 = CSR_READ(sc, WMREG_TARC0);
5132 tarc1 = CSR_READ(sc, WMREG_TARC1);
5139 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
5149 reg = CSR_READ(sc, WMREG_CTRL_EXT);
5161 reg = CSR_READ(sc, WMREG_CTRL_EXT);
5178 reg = CSR_READ(sc, WMREG_GCR);
5188 reg = CSR_READ(sc, WMREG_GCR);
5200 reg = CSR_READ(sc, WMREG_GCR2);
5212 tarc1 = CSR_READ(sc, WMREG_TARC1);
5213 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
5246 reg = CSR_READ(sc, WMREG_CTRL_EXT);
5257 tarc1 = CSR_READ(sc, WMREG_TARC1);
5259 if ((CSR_READ(sc, WMREG_TCTL) & TCTL_MULR) != 0)
5268 reg = CSR_READ(sc, WMREG_STATUS);
5276 reg = CSR_READ(sc, WMREG_IOSFPC);
5285 reg = CSR_READ(sc, WMREG_RFCTL);
5304 reg = CSR_READ(sc, WMREG_RFCTL);
5310 reg = CSR_READ(sc, WMREG_RFCTL);
5328 reg = CSR_READ(sc, WMREG_RFCTL);
5369 reg = CSR_READ(sc, WMREG_CTRL);
5412 reg = CSR_READ(sc, WMREG_FEXTNVM11);
5417 reg = CSR_READ(sc, WMREG_TDLEN(0));
5432 reg = CSR_READ(sc, WMREG_TCTL);
5463 rctl = CSR_READ(sc, WMREG_RCTL);
5468 reg = CSR_READ(sc, WMREG_RXDCTL(0));
5537 sc->sc_pba = CSR_READ(sc, WMREG_RXPBS);
5543 sc->sc_pba = wm_rxpbs_adjust_82580(CSR_READ(sc, WMREG_RXPBS));
5589 if ((CSR_READ(sc, WMREG_STATUS) & STATUS_GIO_M_ENA)
5644 CSR_READ(sc, WMREG_CTRL) | CTRL_PHY_RESET);
5677 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
5692 reg = CSR_READ(sc, WMREG_CTRL) | CTRL_RST;
5699 && ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID)
5724 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
5744 CSR_WRITE(sc, WMREG_CTRL, CSR_READ(sc, WMREG_CTRL) | CTRL_RST);
5762 reg = CSR_READ(sc, WMREG_FEXTNVM3);
5778 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
5805 reg = CSR_READ(sc, WMREG_CTRL_EXT) | CTRL_EXT_EE_RST;
5853 if ((CSR_READ(sc, WMREG_EECD) & EECD_EE_PRES) == 0) {
5875 reg = CSR_READ(sc, WMREG_ICR);
5889 reg = CSR_READ(sc, WMREG_KABGTXD);
5895 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
6046 reta_reg = CSR_READ(sc, WMREG_RETA_Q(i));
6645 crcerrs = CSR_READ(sc, WMREG_CRCERRS);
6646 symerrc = CSR_READ(sc, WMREG_SYMERRC);
6647 mpc = CSR_READ(sc, WMREG_MPC);
6648 colc = CSR_READ(sc, WMREG_COLC);
6649 sec = CSR_READ(sc, WMREG_SEC);
6650 rlec = CSR_READ(sc, WMREG_RLEC);
6660 algnerrc = CSR_READ(sc, WMREG_ALGNERRC);
6661 rxerrc = CSR_READ(sc, WMREG_RXERRC);
6665 cexterr = CSR_READ(sc, WMREG_CEXTERR);
6671 CSR_READ(sc, WMREG_HTDPMC));
6674 WM_EVCNT_ADD(&sc->sc_ev_tncrs, CSR_READ(sc, WMREG_TNCRS));
6675 WM_EVCNT_ADD(&sc->sc_ev_tsctc, CSR_READ(sc, WMREG_TSCTC));
6678 CSR_READ(sc, WMREG_TSCTFC));
6681 CSR_READ(sc, WMREG_CBRDPC));
6683 CSR_READ(sc, WMREG_CBRMPC));
6689 WM_EVCNT_ADD(&sc->sc_ev_rx_xon, CSR_READ(sc, WMREG_XONRXC));
6690 WM_EVCNT_ADD(&sc->sc_ev_tx_xon, CSR_READ(sc, WMREG_XONTXC));
6691 WM_EVCNT_ADD(&sc->sc_ev_rx_xoff, CSR_READ(sc, WMREG_XOFFRXC));
6692 WM_EVCNT_ADD(&sc->sc_ev_tx_xoff, CSR_READ(sc, WMREG_XOFFTXC));
6693 WM_EVCNT_ADD(&sc->sc_ev_rx_macctl, CSR_READ(sc, WMREG_FCRUC));
6696 WM_EVCNT_ADD(&sc->sc_ev_scc, CSR_READ(sc, WMREG_SCC));
6697 WM_EVCNT_ADD(&sc->sc_ev_ecol, CSR_READ(sc, WMREG_ECOL));
6698 WM_EVCNT_ADD(&sc->sc_ev_mcc, CSR_READ(sc, WMREG_MCC));
6699 WM_EVCNT_ADD(&sc->sc_ev_latecol, CSR_READ(sc, WMREG_LATECOL));
6702 WM_EVCNT_ADD(&sc->sc_ev_cbtmpc, CSR_READ(sc, WMREG_CBTMPC));
6705 WM_EVCNT_ADD(&sc->sc_ev_dc, CSR_READ(sc, WMREG_DC));
6706 WM_EVCNT_ADD(&sc->sc_ev_prc64, CSR_READ(sc, WMREG_PRC64));
6707 WM_EVCNT_ADD(&sc->sc_ev_prc127, CSR_READ(sc, WMREG_PRC127));
6708 WM_EVCNT_ADD(&sc->sc_ev_prc255, CSR_READ(sc, WMREG_PRC255));
6709 WM_EVCNT_ADD(&sc->sc_ev_prc511, CSR_READ(sc, WMREG_PRC511));
6710 WM_EVCNT_ADD(&sc->sc_ev_prc1023, CSR_READ(sc, WMREG_PRC1023));
6711 WM_EVCNT_ADD(&sc->sc_ev_prc1522, CSR_READ(sc, WMREG_PRC1522));
6712 WM_EVCNT_ADD(&sc->sc_ev_gprc, CSR_READ(sc, WMREG_GPRC));
6713 WM_EVCNT_ADD(&sc->sc_ev_bprc, CSR_READ(sc, WMREG_BPRC));
6714 WM_EVCNT_ADD(&sc->sc_ev_mprc, CSR_READ(sc, WMREG_MPRC));
6715 WM_EVCNT_ADD(&sc->sc_ev_gptc, CSR_READ(sc, WMREG_GPTC));
6718 CSR_READ(sc, WMREG_GORCL) +
6719 ((uint64_t)CSR_READ(sc, WMREG_GORCH) << 32));
6721 CSR_READ(sc, WMREG_GOTCL) +
6722 ((uint64_t)CSR_READ(sc, WMREG_GOTCH) << 32));
6724 WM_EVCNT_ADD(&sc->sc_ev_rnbc, CSR_READ(sc, WMREG_RNBC));
6725 WM_EVCNT_ADD(&sc->sc_ev_ruc, CSR_READ(sc, WMREG_RUC));
6726 WM_EVCNT_ADD(&sc->sc_ev_rfc, CSR_READ(sc, WMREG_RFC));
6727 WM_EVCNT_ADD(&sc->sc_ev_roc, CSR_READ(sc, WMREG_ROC));
6728 WM_EVCNT_ADD(&sc->sc_ev_rjc, CSR_READ(sc, WMREG_RJC));
6731 WM_EVCNT_ADD(&sc->sc_ev_mgtprc, CSR_READ(sc, WMREG_MGTPRC));
6732 WM_EVCNT_ADD(&sc->sc_ev_mgtpdc, CSR_READ(sc, WMREG_MGTPDC));
6733 WM_EVCNT_ADD(&sc->sc_ev_mgtptc, CSR_READ(sc, WMREG_MGTPTC));
6744 CSR_READ(sc, WMREG_TORL) +
6745 ((uint64_t)CSR_READ(sc, WMREG_TORH) << 32));
6747 CSR_READ(sc, WMREG_TOTL) +
6748 ((uint64_t)CSR_READ(sc, WMREG_TOTH) << 32));
6750 WM_EVCNT_ADD(&sc->sc_ev_tpr, CSR_READ(sc, WMREG_TPR));
6751 WM_EVCNT_ADD(&sc->sc_ev_tpt, CSR_READ(sc, WMREG_TPT));
6752 WM_EVCNT_ADD(&sc->sc_ev_ptc64, CSR_READ(sc, WMREG_PTC64));
6753 WM_EVCNT_ADD(&sc->sc_ev_ptc127, CSR_READ(sc, WMREG_PTC127));
6754 WM_EVCNT_ADD(&sc->sc_ev_ptc255, CSR_READ(sc, WMREG_PTC255));
6755 WM_EVCNT_ADD(&sc->sc_ev_ptc511, CSR_READ(sc, WMREG_PTC511));
6756 WM_EVCNT_ADD(&sc->sc_ev_ptc1023, CSR_READ(sc, WMREG_PTC1023));
6757 WM_EVCNT_ADD(&sc->sc_ev_ptc1522, CSR_READ(sc, WMREG_PTC1522));
6758 WM_EVCNT_ADD(&sc->sc_ev_mptc, CSR_READ(sc, WMREG_MPTC));
6759 WM_EVCNT_ADD(&sc->sc_ev_bptc, CSR_READ(sc, WMREG_BPTC));
6761 WM_EVCNT_ADD(&sc->sc_ev_iac, CSR_READ(sc, WMREG_IAC));
6763 WM_EVCNT_ADD(&sc->sc_ev_icrxptc, CSR_READ(sc, WMREG_ICRXPTC));
6764 WM_EVCNT_ADD(&sc->sc_ev_icrxatc, CSR_READ(sc, WMREG_ICRXATC));
6765 WM_EVCNT_ADD(&sc->sc_ev_ictxptc, CSR_READ(sc, WMREG_ICTXPTC));
6766 WM_EVCNT_ADD(&sc->sc_ev_ictxatc, CSR_READ(sc, WMREG_ICTXATC));
6767 WM_EVCNT_ADD(&sc->sc_ev_ictxqec, CSR_READ(sc, WMREG_ICTXQEC));
6769 CSR_READ(sc, WMREG_ICTXQMTC));
6771 CSR_READ(sc, WMREG_ICRXDMTC));
6772 WM_EVCNT_ADD(&sc->sc_ev_icrxoc, CSR_READ(sc, WMREG_ICRXOC));
6774 WM_EVCNT_ADD(&sc->sc_ev_rpthc, CSR_READ(sc, WMREG_RPTHC));
6775 WM_EVCNT_ADD(&sc->sc_ev_debug1, CSR_READ(sc, WMREG_DEBUG1));
6776 WM_EVCNT_ADD(&sc->sc_ev_debug2, CSR_READ(sc, WMREG_DEBUG2));
6777 WM_EVCNT_ADD(&sc->sc_ev_debug3, CSR_READ(sc, WMREG_DEBUG3));
6778 WM_EVCNT_ADD(&sc->sc_ev_hgptc, CSR_READ(sc, WMREG_HGPTC));
6779 WM_EVCNT_ADD(&sc->sc_ev_debug4, CSR_READ(sc, WMREG_DEBUG4));
6780 WM_EVCNT_ADD(&sc->sc_ev_rxdmtc, CSR_READ(sc, WMREG_RXDMTC));
6781 WM_EVCNT_ADD(&sc->sc_ev_htcbdpc, CSR_READ(sc, WMREG_HTCBDPC));
6784 CSR_READ(sc, WMREG_HGORCL) +
6785 ((uint64_t)CSR_READ(sc, WMREG_HGORCH) << 32));
6787 CSR_READ(sc, WMREG_HGOTCL) +
6788 ((uint64_t)CSR_READ(sc, WMREG_HGOTCH) << 32));
6789 WM_EVCNT_ADD(&sc->sc_ev_lenerrs, CSR_READ(sc, WMREG_LENERRS));
6790 WM_EVCNT_ADD(&sc->sc_ev_scvpc, CSR_READ(sc, WMREG_SCVPC));
6791 WM_EVCNT_ADD(&sc->sc_ev_hrmpc, CSR_READ(sc, WMREG_HRMPC));
6797 rqdpc = CSR_READ(sc, WMREG_RQDPC(i));
6810 WM_EVCNT_ADD(&sc->sc_ev_tlpic, CSR_READ(sc, WMREG_TLPIC));
6811 WM_EVCNT_ADD(&sc->sc_ev_rlpic, CSR_READ(sc, WMREG_RLPIC));
6812 if ((CSR_READ(sc, WMREG_MANC) & MANC_EN_BMC2OS) != 0) {
6814 CSR_READ(sc, WMREG_B2OGPRC));
6816 CSR_READ(sc, WMREG_O2BSPC));
6818 CSR_READ(sc, WMREG_B2OSPC));
6820 CSR_READ(sc, WMREG_O2BGPTC));
7064 if_statadd2(ifp, if_collisions, CSR_READ(sc, WMREG_COLC),
7065 if_ierrors, CSR_READ(sc, WMREG_RXERRC));
7093 reg = CSR_READ(sc, WMREG_GCR);
7107 reg = CSR_READ(sc, WMREG_FFLT_DBG);
7116 reg = CSR_READ(sc, WMREG_CTRL_EXT);
7241 reg = CSR_READ(sc, WMREG_CTRL_EXT);
7259 reg = CSR_READ(sc, WMREG_RXCSUM);
7277 reg = CSR_READ(sc, WMREG_CTRL_EXT);
7293 reg = CSR_READ(sc, WMREG_CTRL_EXT);
7303 reg = CSR_READ(sc, WMREG_RFCTL);
7340 ivar = CSR_READ(sc, WMREG_IVAR_Q(qid));
7359 ivar = CSR_READ(sc,
7392 reg = CSR_READ(sc, WMREG_RXCSUM);
7492 reg = CSR_READ(sc, WMREG_TCTL_EXT);
7557 reg = CSR_READ(sc, WMREG_PBA_ECC);
7565 reg = CSR_READ(sc, WMREG_PBECCSTS);
7786 if (CSR_READ(sc, WMREG_TDT(0)) == CSR_READ(sc, WMREG_TDH(0)) &&
7787 CSR_READ(sc, WMREG_TDFT) == CSR_READ(sc, WMREG_TDFH) &&
7788 CSR_READ(sc, WMREG_TDFTS) == CSR_READ(sc, WMREG_TDFHS)) {
7794 uint32_t tctl = CSR_READ(sc, WMREG_TCTL);
10429 status = CSR_READ(sc, WMREG_STATUS);
10552 tipg_reg = CSR_READ(sc, WMREG_TIPG);
10658 reg = CSR_READ(sc, WMREG_FEXTNVM4);
10685 reg = CSR_READ(sc, WMREG_FEXTNVM6);
10686 if (CSR_READ(sc, WMREG_PCIEANACFG) & FEXTNVM6_K1_OFF_ENABLE)
10727 status = CSR_READ(sc, WMREG_STATUS);
10739 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
10787 reg = CSR_READ(sc, WMREG_PCS_LSTS);
10810 reg = CSR_READ(sc, WMREG_PCS_LSTS);
10816 pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
10817 pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
10912 icr = CSR_READ(sc, WMREG_ICR);
11178 reg = CSR_READ(sc, WMREG_ICR);
11305 reg = CSR_READ(sc, WMREG_CTRL_EXT);
11734 reg = CSR_READ(sc, WMREG_MDIC);
11742 reg = CSR_READ(sc, WMREG_MDICNFG);
11825 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
11927 reg = CSR_READ(sc, WMREG_PHPM);
12041 v = CSR_READ(sc, WMREG_CTRL);
12068 v = CSR_READ(sc, WMREG_CTRL);
12087 if (CSR_READ(sc, WMREG_CTRL) & MDI_IO)
12172 mdic = CSR_READ(sc, WMREG_MDIC);
12225 mdic = CSR_READ(sc, WMREG_MDIC);
12700 && ((CSR_READ(sc, WMREG_PHY_CTRL) & PHY_CTRL_GBE_DIS) == 0)) {
13138 *val = CSR_READ(sc, WMREG_KUMCTRLSTA) & KUMCTRLSTA_MASK;
13235 reg = CSR_READ(sc, WMREG_MDIC);
13243 reg = CSR_READ(sc, WMREG_MDICNFG);
13324 i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
13387 i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
13484 status = CSR_READ(sc, WMREG_STATUS);
13575 ctrl = CSR_READ(sc, WMREG_CTRL);
13585 if (CSR_READ(sc, WMREG_STATUS) & STATUS_LU)
13593 status = CSR_READ(sc, WMREG_STATUS);
13609 sc->sc_ctrl = CSR_READ(sc, WMREG_CTRL);
13618 if (CSR_READ(sc, WMREG_CTRL) & CTRL_TFCE)
13659 status = CSR_READ(sc, WMREG_STATUS);
13671 if (CSR_READ(sc, WMREG_STATUS) & STATUS_FD)
13675 ctrl = CSR_READ(sc, WMREG_CTRL);
13703 rxcw = CSR_READ(sc, WMREG_RXCW);
13704 ctrl = CSR_READ(sc, WMREG_CTRL);
13705 status = CSR_READ(sc, WMREG_STATUS);
13776 status = CSR_READ(sc, WMREG_STATUS);
13779 (void)CSR_READ(sc, WMREG_RXCW);
13780 (void)CSR_READ(sc, WMREG_CTRL);
13840 reg = CSR_READ(sc, WMREG_PCS_CFG);
13845 reg = CSR_READ(sc, WMREG_CTRL_EXT);
13871 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
13881 reg = CSR_READ(sc, WMREG_CONNSW);
13886 pcs_lctl = CSR_READ(sc, WMREG_PCS_LCTL);
13922 reg = CSR_READ(sc, WMREG_PCS_ANADV);
13946 reg = CSR_READ(sc, WMREG_PCS_LSTS);
13958 status = CSR_READ(sc, WMREG_STATUS);
13989 reg = CSR_READ(sc, WMREG_PCS_LSTS);
13995 pcs_adv = CSR_READ(sc, WMREG_PCS_ANADV);
13996 pcs_lpab = CSR_READ(sc, WMREG_PCS_LPAB);
14042 reg = CSR_READ(sc, WMREG_PCS_LSTS);
14084 i2ccmd = CSR_READ(sc, WMREG_I2CCMD);
14107 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
14181 reg = CSR_READ(sc, WMREG_EECD);
14211 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_DI;
14218 if (CSR_READ(sc, WMREG_EECD) & EECD_DO)
14249 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_DI);
14286 reg = CSR_READ(sc, WMREG_EECD) & ~EECD_CS;
14309 reg = CSR_READ(sc, WMREG_EECD);
14413 reg = CSR_READ(sc, WMREG_EECD) & ~(EECD_SK | EECD_CS);
14442 reg = (CSR_READ(sc, WMREG_EECD) & ~EECD_SK) | EECD_CS;
14462 reg = CSR_READ(sc, rw);
14496 data[i] = (CSR_READ(sc, WMREG_EERD) >> EERD_DATA_SHIFT);
14548 eecd = CSR_READ(sc, WMREG_EECD);
15016 invm_dword = CSR_READ(sc, WM_INVM_DATA_REG(i));
15124 eecd = CSR_READ(sc, WMREG_EECD);
15141 eec = CSR_READ(sc, WMREG_EEC);
15236 dword = CSR_READ(sc, WM_INVM_DATA_REG(61));
15442 reg = CSR_READ(sc, WMREG_EECD);
15450 reg = CSR_READ(sc, WMREG_EECD);
15501 reg = CSR_READ(sc, WMREG_EECD);
15514 reg = CSR_READ(sc, WMREG_EECD);
15539 swsm = CSR_READ(sc, WMREG_SWSM);
15566 swsm = CSR_READ(sc, WMREG_SWSM);
15570 swsm = CSR_READ(sc, WMREG_SWSM);
15600 swsm = CSR_READ(sc, WMREG_SWSM);
15632 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
15660 swfw_sync = CSR_READ(sc, WMREG_SW_FW_SYNC);
15782 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
15786 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
15805 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
15822 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
15836 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
15861 ext_ctrl = CSR_READ(sc, WMREG_EXTCNFCTR);
15900 reg = CSR_READ(sc, WMREG_EXTCNFCTR);
15904 reg = CSR_READ(sc, WMREG_EXTCNFCTR);
15929 reg = CSR_READ(sc, WMREG_EXTCNFCTR);
15981 fwsm = CSR_READ(sc, WMREG_FWSM);
16008 fwsm = CSR_READ(sc, WMREG_FWSM);
16025 manc = CSR_READ(sc, WMREG_MANC);
16033 fwsm = CSR_READ(sc, WMREG_FWSM);
16034 factps = CSR_READ(sc, WMREG_FACTPS);
16041 factps = CSR_READ(sc, WMREG_FACTPS);
16077 reg = CSR_READ(sc, WMREG_FWSM);
16093 reg = CSR_READ(sc, WMREG_MANC);
16116 reg = CSR_READ(sc, WMREG_SWSM);
16119 reg = CSR_READ(sc, WMREG_CTRL_EXT);
16133 reg = CSR_READ(sc, WMREG_SWSM);
16136 reg = CSR_READ(sc, WMREG_CTRL_EXT);
16152 reg = CSR_READ(sc, WMREG_EXTCNFCTR);
16189 fwsm = CSR_READ(sc, WMREG_FWSM);
16201 reg = CSR_READ(sc, WMREG_CTRL_EXT);
16238 reg = CSR_READ(sc, WMREG_CTRL_EXT);
16298 uint32_t manc2h = CSR_READ(sc, WMREG_MANC2H);
16299 uint32_t manc = CSR_READ(sc, WMREG_MANC);
16320 uint32_t manc = CSR_READ(sc, WMREG_MANC);
16346 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_MODE) != 0)
16405 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) != 0) {
16407 reg = CSR_READ(sc, WMREG_H2ME);
16413 while ((CSR_READ(sc, WMREG_FWSM) & FWSM_ULP_CFG_DONE) != 0) {
16421 reg = CSR_READ(sc, WMREG_H2ME);
16446 reg2 = CSR_READ(sc, WMREG_CTRL_EXT);
16460 reg = CSR_READ(sc, WMREG_CTRL_EXT);
16486 reg = CSR_READ(sc, WMREG_FEXTNVM7);
16536 mreg = CSR_READ(sc, WMREG_CORDOVA_MTA + (i * 4));
16545 mreg = CSR_READ(sc, WMREG_RCTL);
16558 mreg = CSR_READ(sc, WMREG_CTRL);
16593 reg = CSR_READ(sc, WMREG_PHY_CTRL);
16643 phy_ctrl = CSR_READ(sc, WMREG_PHY_CTRL);
16657 CSR_READ(sc, WMREG_FEXTNVM6)
16774 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
16827 reg = CSR_READ(sc, WMREG_CTRL_EXT);
16840 reg = CSR_READ(sc, WMREG_WUFC) | WUFC_MAG;
16842 CSR_WRITE(sc, WMREG_RCTL, CSR_READ(sc, WMREG_RCTL) | RCTL_MPE);
16963 reg = CSR_READ(sc, WMREG_PHPM);
16972 reg = CSR_READ(sc, WMREG_PHY_CTRL);
17007 ipcnfg = CSR_READ(sc, WMREG_IPCNFG);
17008 eeer = CSR_READ(sc, WMREG_EEER);
17021 CSR_READ(sc, WMREG_IPCNFG); /* XXX flush? */
17022 CSR_READ(sc, WMREG_EEER); /* XXX flush? */
17144 uint32_t status = CSR_READ(sc, WMREG_STATUS);
17177 reg = CSR_READ(sc, WMREG_PHY_CTRL);
17354 mac_reg = CSR_READ(sc, WMREG_CORDOVA_RAL(i));
17360 mac_reg = CSR_READ(sc, WMREG_CORDOVA_RAH(i));
17414 addr_high = CSR_READ(sc, WMREG_CORDOVA_RAH(i));
17417 addr_low = CSR_READ(sc, WMREG_CORDOVA_RAL(i));
17438 mac_reg = CSR_READ(sc, WMREG_FFLT_DBG);
17446 mac_reg = CSR_READ(sc, WMREG_RCTL);
17593 uint32_t fextnvm6 = CSR_READ(sc, WMREG_FEXTNVM6);
17594 uint32_t status = CSR_READ(sc, WMREG_STATUS);
17734 reg = CSR_READ(sc, WMREG_FEXTNVM4);
17835 KASSERT(CSR_READ(sc, WMREG_EXTCNFCTR) & EXTCNFCTR_MDIO_SW_OWNERSHIP);
17852 ctrl = CSR_READ(sc, WMREG_CTRL);
17853 ctrl_ext = CSR_READ(sc, WMREG_CTRL_EXT);
17922 reg = CSR_READ(sc, WMREG_MDICNFG);
17941 KASSERT(CSR_READ(sc, WMREG_EXTCNFCTR) & EXTCNFCTR_MDIO_SW_OWNERSHIP);
17977 if ((CSR_READ(sc, WMREG_FWSM) & FWSM_FW_VALID) == 0) {
17988 reg = CSR_READ(sc, WMREG_CTRL_EXT);
18003 reg = CSR_READ(sc, WMREG_FEXTNVM3);
18009 reg = CSR_READ(sc, WMREG_CTRL);
18026 } while (((CSR_READ(sc, WMREG_CTRL_EXT) & CTRL_EXT_LPCD) == 0)
18052 status = CSR_READ(sc, WMREG_STATUS);
18070 rxa = CSR_READ(sc, WMREG_PBA) & PBA_RXA_MASK;
18135 reg = CSR_READ(sc, WMREG_SVT) & ~SVT_OFF_HWM;
18140 reg = CSR_READ(sc, WMREG_SVCR);
18171 wuc = CSR_READ(sc, WMREG_WUC);
18172 mdicnfg = CSR_READ(sc, WMREG_MDICNFG);
18198 reg = CSR_READ(sc, WMREG_CTRL);
18201 reg = CSR_READ(sc, WMREG_CTRL_EXT);
18243 reg = CSR_READ(sc, WMREG_FEXTNVM7);
18247 reg = CSR_READ(sc, WMREG_FEXTNVM9);
18262 reg = CSR_READ(sc, WMREG_TDH(wmq->wmq_id));
18276 reg = CSR_READ(sc, WMREG_TDT(wmq->wmq_id));
18298 device_printf(sc->sc_dev, "TARC0: %08x\n", CSR_READ(sc, WMREG_TARC0));
18299 device_printf(sc->sc_dev, "TDT0: %08x\n", CSR_READ(sc, WMREG_TDT(0)));