Lines Matching defs:mcr
871 uint16_t mcr;
873 mcr = CSR_READ_2(sc, VTE_MCR0);
874 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX);
876 mcr |= MCR0_FULL_DUPLEX;
879 mcr |= MCR0_FC_ENB;
887 mcr |= MCR0_FC_ENB;
890 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1208 uint16_t mcr, mdcsc;
1212 mcr = CSR_READ_2(sc, VTE_MCR1);
1213 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);
1220 aprint_error_dev(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr);
1447 uint16_t mcr;
1451 mcr = CSR_READ_2(sc, VTE_MCR0);
1452 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) !=
1455 mcr |= MCR0_RX_ENB | MCR0_TX_ENB;
1456 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1458 mcr = CSR_READ_2(sc, VTE_MCR0);
1459 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) ==
1466 "could not enable RX/TX MAC(0x%04x)!\n", mcr);
1474 uint16_t mcr;
1478 mcr = CSR_READ_2(sc, VTE_MCR0);
1479 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) {
1480 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB);
1481 CSR_WRITE_2(sc, VTE_MCR0, mcr);
1483 mcr = CSR_READ_2(sc, VTE_MCR0);
1484 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0)
1490 "could not disable RX/TX MAC(0x%04x)!\n", mcr);
1585 uint16_t mchash[4], mcr;
1598 mcr = CSR_READ_2(sc, VTE_MCR0);
1599 DPRINTF(("vte_rxfilter mcr 0x%x\n", mcr));
1600 mcr &= ~(MCR0_PROMISC | MCR0_BROADCAST_DIS | MCR0_MULTICAST);
1602 mcr |= MCR0_BROADCAST_DIS;
1605 mcr |= MCR0_PROMISC;
1607 mcr |= MCR0_MULTICAST;
1622 mcr |= MCR0_MULTICAST;
1650 mcr |= MCR0_MULTICAST;
1669 DPRINTF(("chipit mcr0 0x%x\n", mcr));
1670 CSR_WRITE_2(sc, VTE_MCR0, mcr);