Lines Matching refs:rtwn_bb_write
183 #define rtwn_bb_write rtwn_write_4 macro
832 rtwn_bb_write(sc, R92C_LSSI_PARAM(chain), in rtwn_rf_write()
845 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), in rtwn_rf_read()
849 rtwn_bb_write(sc, R92C_HSSI_PARAM2(chain), in rtwn_rf_read()
854 rtwn_bb_write(sc, R92C_HSSI_PARAM2(0), in rtwn_rf_read()
1380 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); in rtwn_newstate()
1384 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); in rtwn_newstate()
1421 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg); in rtwn_newstate()
1429 rtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg); in rtwn_newstate()
2701 rtwn_bb_write(sc, prog->regs[i], prog->vals[i]); in rtwn_bb_init()
2709 rtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg); in rtwn_bb_init()
2713 rtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg); in rtwn_bb_init()
2717 rtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg); in rtwn_bb_init()
2721 rtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg); in rtwn_bb_init()
2725 rtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg); in rtwn_bb_init()
2729 rtwn_bb_write(sc, 0xe74, reg); in rtwn_bb_init()
2732 rtwn_bb_write(sc, 0xe78, reg); in rtwn_bb_init()
2735 rtwn_bb_write(sc, 0xe7c, reg); in rtwn_bb_init()
2738 rtwn_bb_write(sc, 0xe80, reg); in rtwn_bb_init()
2741 rtwn_bb_write(sc, 0xe88, reg); in rtwn_bb_init()
2746 rtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE, in rtwn_bb_init()
2786 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); in rtwn_rf_init()
2791 rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg); in rtwn_rf_init()
2796 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); in rtwn_rf_init()
2800 rtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg); in rtwn_rf_init()
2822 rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg); in rtwn_rf_init()
2924 rtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg); in rtwn_write_txpower()
2929 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); in rtwn_write_txpower()
2935 rtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg); in rtwn_write_txpower()
2938 rtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg); in rtwn_write_txpower()
2941 rtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain), in rtwn_write_txpower()
2946 rtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain), in rtwn_write_txpower()
2952 rtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain), in rtwn_write_txpower()
2957 rtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain), in rtwn_write_txpower()
2962 rtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain), in rtwn_write_txpower()
2967 rtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain), in rtwn_write_txpower()
3125 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, in rtwn_set_chan()
3127 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, in rtwn_set_chan()
3133 rtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg); in rtwn_set_chan()
3137 rtwn_bb_write(sc, R92C_OFDM1_LSTF, reg); in rtwn_set_chan()
3139 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, in rtwn_set_chan()
3145 rtwn_bb_write(sc, 0x818, reg); in rtwn_set_chan()
3156 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, in rtwn_set_chan()
3158 rtwn_bb_write(sc, R92C_FPGA1_RFMOD, in rtwn_set_chan()
3161 rtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2, in rtwn_set_chan()
3358 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); in rtwn_init()
3361 rtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg); in rtwn_init()