184 #define rtwn_bb_read	rtwn_read_4  macro
841 	reg[0] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(0));  in rtwn_rf_read()
843 		reg[chain] = rtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));  in rtwn_rf_read()
858 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)  in rtwn_rf_read()
859 		val = rtwn_bb_read(sc, R92C_HSPI_READBACK(chain));  in rtwn_rf_read()
861 		val = rtwn_bb_read(sc, R92C_LSSI_READBACK(chain));  in rtwn_rf_read()
1378 			reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));  in rtwn_newstate()
1382 			reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));  in rtwn_newstate()
1415 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));  in rtwn_newstate()
1423 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));  in rtwn_newstate()
2707 		reg = rtwn_bb_read(sc, R92C_FPGA0_TXINFO);  in rtwn_bb_init()
2711 		reg = rtwn_bb_read(sc, R92C_FPGA1_TXINFO);  in rtwn_bb_init()
2715 		reg = rtwn_bb_read(sc, R92C_CCK0_AFESETTING);  in rtwn_bb_init()
2719 		reg = rtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);  in rtwn_bb_init()
2723 		reg = rtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);  in rtwn_bb_init()
2727 		reg = rtwn_bb_read(sc, 0xe74);  in rtwn_bb_init()
2730 		reg = rtwn_bb_read(sc, 0xe78);  in rtwn_bb_init()
2733 		reg = rtwn_bb_read(sc, 0xe7c);  in rtwn_bb_init()
2736 		reg = rtwn_bb_read(sc, 0xe80);  in rtwn_bb_init()
2739 		reg = rtwn_bb_read(sc, 0xe88);  in rtwn_bb_init()
2751 	if (rtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &  in rtwn_bb_init()
2780 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));  in rtwn_rf_init()
2784 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));  in rtwn_rf_init()
2789 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));  in rtwn_rf_init()
2794 		reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));  in rtwn_rf_init()
2798 		reg = rtwn_bb_read(sc, R92C_HSSI_PARAM2(i));  in rtwn_rf_init()
2820 		reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));  in rtwn_rf_init()
2922 		reg = rtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);  in rtwn_write_txpower()
2925 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);  in rtwn_write_txpower()
2931 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);  in rtwn_write_txpower()
2936 		reg = rtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);  in rtwn_write_txpower()
3126 		    rtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);  in rtwn_set_chan()
3128 		    rtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);  in rtwn_set_chan()
3131 		reg = rtwn_bb_read(sc, R92C_CCK0_SYSTEM);  in rtwn_set_chan()
3135 		reg = rtwn_bb_read(sc, R92C_OFDM1_LSTF);  in rtwn_set_chan()
3140 		    rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &  in rtwn_set_chan()
3143 		reg = rtwn_bb_read(sc, 0x818);  in rtwn_set_chan()
3157 		    rtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);  in rtwn_set_chan()
3159 		    rtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);  in rtwn_set_chan()
3162 		    rtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |  in rtwn_set_chan()
3356 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);  in rtwn_init()
3359 	reg = rtwn_bb_read(sc, R92C_FPGA0_RFMOD);  in rtwn_init()