Lines Matching defs:sc
68 MCLGETL(struct rge_softc *sc __unused, int how,
189 struct rge_softc *sc = device_private(self);
205 sc->sc_dev = self;
213 PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rge_btag, &sc->rge_bhandle,
214 NULL, &sc->rge_bsize)) {
216 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rge_btag,
217 &sc->rge_bhandle, NULL, &sc->rge_bsize)) {
219 0, &sc->rge_btag, &sc->rge_bhandle, NULL,
220 &sc->rge_bsize)) {
243 sc->rge_flags |= RGE_FLAG_MSI;
249 sc->sc_ih = pci_intr_establish_xname(pc, ihp[0], IPL_NET, rge_intr,
250 sc, device_xname(sc->sc_dev));
251 if (sc->sc_ih == NULL) {
252 aprint_error_dev(sc->sc_dev, ": couldn't establish interrupt");
258 aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
261 sc->sc_dmat = pa->pa_dmat64;
263 sc->sc_dmat = pa->pa_dmat;
265 sc->sc_pc = pa->pa_pc;
266 sc->sc_tag = pa->pa_tag;
269 hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV;
272 sc->rge_type = MAC_CFG2;
276 sc->rge_type = MAC_CFG3;
280 sc->rge_type = MAC_CFG4;
284 sc->rge_type = MAC_CFG5;
292 aprint_normal_dev(sc->sc_dev, "HW rev. %s\n", revstr);
293 rge_config_imtype(sc, RGE_IMTYPE_SIM);
309 rge_exit_oob(sc);
310 rge_hw_init(sc);
312 rge_get_macaddr(sc, eaddr);
313 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
316 memcpy(sc->sc_enaddr, eaddr, ETHER_ADDR_LEN);
318 rge_set_phy_power(sc, 1);
319 rge_phy_config(sc);
321 if (rge_allocmem(sc))
324 ifp = &sc->sc_ec.ec_if;
325 ifp->if_softc = sc;
326 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
344 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_MTU;
345 sc->sc_ec.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING;
347 callout_init(&sc->sc_timeout, CALLOUT_FLAGS);
348 callout_setfunc(&sc->sc_timeout, rge_tick, sc);
355 sc->sc_ec.ec_ifmedia = &sc->sc_media;
356 ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd,
358 rge_add_media_types(sc);
359 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL);
360 ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO);
361 sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media;
376 struct rge_softc *sc = arg;
377 struct ifnet *ifp = &sc->sc_ec.ec_if;
385 RGE_WRITE_4(sc, RGE_IMR, 0);
387 if (!(sc->rge_flags & RGE_FLAG_MSI)) {
388 if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0)
392 status = RGE_READ_4(sc, RGE_ISR);
394 RGE_WRITE_4(sc, RGE_ISR, status);
400 if (status & sc->rge_intrs) {
402 (sc->rge_rx_ack | RGE_ISR_RX_ERR | RGE_ISR_RX_FIFO_OFLOW)) {
403 rx |= rge_rxeof(sc);
407 if (status & (sc->rge_tx_ack | RGE_ISR_TX_ERR)) {
408 tx |= rge_txeof(sc);
420 if (sc->rge_timerintr) {
426 rge_setup_intr(sc, RGE_IMTYPE_NONE);
433 rge_rxeof(sc);
434 rge_txeof(sc);
436 RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
443 rge_setup_intr(sc, RGE_IMTYPE_SIM);
446 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs);
452 rge_encap(struct rge_softc *sc, struct mbuf *m, int idx)
476 txq = &sc->rge_ldata.rge_txq[idx];
479 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m, BUS_DMA_NOWAIT);
485 bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m,
494 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize,
507 d = &sc->rge_ldata.rge_tx_list[cur];
529 d = &sc->rge_ldata.rge_tx_list[idx];
533 bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map,
547 struct rge_softc *sc = ifp->if_softc;
576 rge_iff(sc);
587 struct rge_softc *sc = ifp->if_softc;
601 idx = sc->rge_ldata.rge_txq_prodidx;
602 free = sc->rge_ldata.rge_txq_considx;
617 used = rge_encap(sc, m, idx);
641 sc->rge_ldata.rge_txq_prodidx = idx;
642 rge_txstart(sc);
648 struct rge_softc *sc = ifp->if_softc;
650 device_printf(sc->sc_dev, "watchdog timeout\n");
659 struct rge_softc *sc = ifp->if_softc;
666 rge_set_macaddr(sc, CLLADDR(ifp->if_sadl));
669 RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN);
672 int error = rge_rx_list_init(sc);
674 device_printf(sc->sc_dev,
681 rge_tx_list_init(sc);
684 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO,
685 RGE_ADDR_LO(sc->rge_ldata.rge_rx_list_map->dm_segs[0].ds_addr));
686 RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI,
687 RGE_ADDR_HI(sc->rge_ldata.rge_rx_list_map->dm_segs[0].ds_addr));
688 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO,
689 RGE_ADDR_LO(sc->rge_ldata.rge_tx_list_map->dm_segs[0].ds_addr));
690 RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI,
691 RGE_ADDR_HI(sc->rge_ldata.rge_tx_list_map->dm_segs[0].ds_addr));
693 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
695 RGE_CLRBIT_1(sc, 0xf1, 0x80);
696 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
697 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
698 RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_RDY_TO_L23);
702 RGE_WRITE_4(sc, RGE_INTMITI(i), 0);
705 RGE_WRITE_4(sc, RGE_RXCFG, RGE_RXCFG_CONFIG);
706 RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG);
708 val = rge_read_csi(sc, 0x70c) & ~0xff000000;
709 rge_write_csi(sc, 0x70c, val | 0x27000000);
712 val = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x78) & ~0x00007000;
713 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x78, val | 0x00005000);
715 RGE_WRITE_2(sc, 0x0382, 0x221b);
716 RGE_WRITE_1(sc, 0x4500, 0);
717 RGE_WRITE_2(sc, 0x4800, 0);
718 RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN);
720 rge_write_mac_ocp(sc, 0xc140, 0xffff);
721 rge_write_mac_ocp(sc, 0xc142, 0xffff);
723 val = rge_read_mac_ocp(sc, 0xd3e2) & ~0x0fff;
724 rge_write_mac_ocp(sc, 0xd3e2, val | 0x03a9);
726 RGE_MAC_CLRBIT(sc, 0xd3e4, 0x00ff);
727 RGE_MAC_SETBIT(sc, 0xe860, 0x0080);
728 RGE_MAC_SETBIT(sc, 0xeb58, 0x0001);
730 val = rge_read_mac_ocp(sc, 0xe614) & ~0x0700;
731 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3)
732 rge_write_mac_ocp(sc, 0xe614, val | 0x0400);
734 rge_write_mac_ocp(sc, 0xe614, val | 0x0200);
736 RGE_MAC_CLRBIT(sc, 0xe63e, 0x0c00);
738 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
739 val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030;
740 rge_write_mac_ocp(sc, 0xe63e, val | 0x0020);
742 RGE_MAC_CLRBIT(sc, 0xe63e, 0x0030);
744 RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c);
746 val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff;
747 rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033);
749 val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0;
750 rge_write_mac_ocp(sc, 0xeb50, val | 0x0040);
752 val = rge_read_mac_ocp(sc, 0xe056) & ~0x00f0;
753 rge_write_mac_ocp(sc, 0xe056, val | 0x0030);
755 RGE_WRITE_1(sc, RGE_TDFNR, 0x10);
757 RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_TX_10M_PS_EN);
759 RGE_MAC_CLRBIT(sc, 0xe040, 0x1000);
761 val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003;
762 rge_write_mac_ocp(sc, 0xea1c, val | 0x0001);
764 val = rge_read_mac_ocp(sc, 0xe0c0) & ~0x4f0f;
765 rge_write_mac_ocp(sc, 0xe0c0, val | 0x4403);
767 RGE_MAC_SETBIT(sc, 0xe052, 0x0068);
768 RGE_MAC_CLRBIT(sc, 0xe052, 0x0080);
770 val = rge_read_mac_ocp(sc, 0xc0ac) & ~0x0080;
771 rge_write_mac_ocp(sc, 0xc0ac, val | 0x1f00);
773 val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff;
774 rge_write_mac_ocp(sc, 0xd430, val | 0x047f);
776 val = rge_read_mac_ocp(sc, 0xe84c) & ~0x0040;
777 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3)
778 rge_write_mac_ocp(sc, 0xe84c, 0x00c0);
780 rge_write_mac_ocp(sc, 0xe84c, 0x0080);
782 RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN);
784 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3)
785 RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01);
788 RGE_MAC_CLRBIT(sc, 0xe080, 0x0002);
790 RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004);
792 RGE_MAC_SETBIT(sc, 0xeb54, 0x0001);
794 RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001);
796 RGE_CLRBIT_4(sc, 0x1880, 0x0030);
798 rge_write_mac_ocp(sc, 0xe098, 0xc302);
800 if ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
801 RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP);
803 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP);
805 RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM);
808 if (!(rge_read_mac_ocp(sc, 0xe00e) & 0x2000))
814 RGE_CLRBIT_1(sc, RGE_PPSW, 0x08);
820 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB);
823 rge_iff(sc);
825 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
826 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
828 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
831 rge_setup_intr(sc, RGE_IMTYPE_SIM);
836 callout_schedule(&sc->sc_timeout, 1);
847 struct rge_softc *sc = ifp->if_softc;
849 callout_halt(&sc->sc_timeout, NULL);
853 sc->rge_timerintr = 0;
855 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
859 RGE_WRITE_4(sc, RGE_IMR, 0);
862 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
863 RGE_WRITE_4(sc, RGE_TIMERINT1, 0);
864 RGE_WRITE_4(sc, RGE_TIMERINT2, 0);
865 RGE_WRITE_4(sc, RGE_TIMERINT3, 0);
867 rge_reset(sc);
869 // intr_barrier(sc->sc_ih);
873 if (sc->rge_head != NULL) {
874 m_freem(sc->rge_head);
875 sc->rge_head = sc->rge_tail = NULL;
878 rge_tx_list_fini(sc);
879 rge_rx_list_fini(sc);
888 struct rge_softc *sc = ifp->if_softc;
889 struct ifmedia *ifm = &sc->sc_media;
896 RGE_PHY_CLRBIT(sc, 0xa428, 0x0200);
897 RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001);
899 val = rge_read_phy_ocp(sc, 0xa5d4);
921 gig = rge_read_phy(sc, 0, MII_100T2CR) &
929 gig = rge_read_phy(sc, 0, MII_100T2CR) &
936 device_printf(sc->sc_dev,
941 rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC);
942 rge_write_phy(sc, 0, MII_100T2CR, gig);
943 rge_write_phy_ocp(sc, 0xa5d4, val);
944 rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
956 struct rge_softc *sc = ifp->if_softc;
962 if (rge_get_link_status(sc)) {
965 status = RGE_READ_2(sc, RGE_PHYSTAT);
990 rge_allocmem(struct rge_softc *sc)
995 error = bus_dmamap_create(sc->sc_dmat, RGE_TX_LIST_SZ, 1,
996 RGE_TX_LIST_SZ, 0, BUS_DMA_NOWAIT, &sc->rge_ldata.rge_tx_list_map);
998 aprint_error_dev(sc->sc_dev, "can't create TX list map\n");
1001 error = bus_dmamem_alloc(sc->sc_dmat, RGE_TX_LIST_SZ, RGE_ALIGN, 0,
1002 &sc->rge_ldata.rge_tx_listseg, 1, &sc->rge_ldata.rge_tx_listnseg,
1005 aprint_error_dev(sc->sc_dev, "can't alloc TX list\n");
1010 error = bus_dmamem_map(sc->sc_dmat, &sc->rge_ldata.rge_tx_listseg,
1011 sc->rge_ldata.rge_tx_listnseg, RGE_TX_LIST_SZ,
1012 (void **) &sc->rge_ldata.rge_tx_list,
1015 aprint_error_dev(sc->sc_dev, "can't map TX dma buffers\n");
1016 bus_dmamem_free(sc->sc_dmat, &sc->rge_ldata.rge_tx_listseg,
1017 sc->rge_ldata.rge_tx_listnseg);
1020 memset(sc->rge_ldata.rge_tx_list, 0, RGE_TX_LIST_SZ);
1021 error = bus_dmamap_load(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map,
1022 sc->rge_ldata.rge_tx_list, RGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
1024 aprint_error_dev(sc->sc_dev, "can't load TX dma map\n");
1025 bus_dmamap_destroy(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map);
1026 bus_dmamem_unmap(sc->sc_dmat,
1027 sc->rge_ldata.rge_tx_list, RGE_TX_LIST_SZ);
1028 bus_dmamem_free(sc->sc_dmat, &sc->rge_ldata.rge_tx_listseg,
1029 sc->rge_ldata.rge_tx_listnseg);
1035 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN,
1037 &sc->rge_ldata.rge_txq[i].txq_dmamap);
1039 aprint_error_dev(sc->sc_dev, "can't create DMA map for TX\n");
1045 error = bus_dmamap_create(sc->sc_dmat, RGE_RX_LIST_SZ, 1,
1046 RGE_RX_LIST_SZ, 0, 0, &sc->rge_ldata.rge_rx_list_map);
1048 aprint_error_dev(sc->sc_dev, "can't create RX list map\n");
1051 error = bus_dmamem_alloc(sc->sc_dmat, RGE_RX_LIST_SZ, RGE_ALIGN, 0,
1052 &sc->rge_ldata.rge_rx_listseg, 1, &sc->rge_ldata.rge_rx_listnseg,
1055 aprint_error_dev(sc->sc_dev, "can't alloc RX list\n");
1060 error = bus_dmamem_map(sc->sc_dmat, &sc->rge_ldata.rge_rx_listseg,
1061 sc->rge_ldata.rge_rx_listnseg, RGE_RX_LIST_SZ,
1062 (void **) &sc->rge_ldata.rge_rx_list,
1065 aprint_error_dev(sc->sc_dev, "can't map RX dma buffers\n");
1066 bus_dmamem_free(sc->sc_dmat, &sc->rge_ldata.rge_rx_listseg,
1067 sc->rge_ldata.rge_rx_listnseg);
1070 memset(sc->rge_ldata.rge_rx_list, 0, RGE_RX_LIST_SZ);
1071 error = bus_dmamap_load(sc->sc_dmat, sc->rge_ldata.rge_rx_list_map,
1072 sc->rge_ldata.rge_rx_list, RGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
1074 aprint_error_dev(sc->sc_dev, "can't load RX dma map\n");
1075 bus_dmamap_destroy(sc->sc_dmat, sc->rge_ldata.rge_rx_list_map);
1076 bus_dmamem_unmap(sc->sc_dmat,
1077 sc->rge_ldata.rge_rx_list, RGE_RX_LIST_SZ);
1078 bus_dmamem_free(sc->sc_dmat, &sc->rge_ldata.rge_rx_listseg,
1079 sc->rge_ldata.rge_rx_listnseg);
1088 error = bus_dmamap_create(sc->sc_dmat, RGE_JUMBO_FRAMELEN, 1,
1090 &sc->rge_ldata.rge_rxq[i].rxq_dmamap);
1092 aprint_error_dev(sc->sc_dev, "can't create DMA map for RX\n");
1104 rge_load_rxbuf(struct rge_softc *sc, int idx)
1106 struct rge_rx_desc *r = &sc->rge_ldata.rge_rx_list[idx];
1107 struct rge_rxq *rxq = &sc->rge_ldata.rge_rxq[idx];
1119 bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_rx_list_map,
1128 rge_newbuf(struct rge_softc *sc, int idx)
1138 MCLAIM(m, &sc->sc_ec.ec_rx_mowner);
1142 rxq = &sc->rge_ldata.rge_rxq[idx];
1146 bus_dmamap_unload(sc->sc_dmat, rxq->rxq_dmamap);
1149 error = bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT);
1152 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize,
1158 rge_load_rxbuf(sc, idx);
1164 rge_rx_list_init(struct rge_softc *sc)
1168 memset(sc->rge_ldata.rge_rx_list, 0, RGE_RX_LIST_SZ);
1171 sc->rge_ldata.rge_rxq[i].rxq_mbuf = NULL;
1172 if (rge_newbuf(sc, i) != 0) {
1173 rge_rx_list_fini(sc);
1178 sc->rge_ldata.rge_rxq_prodidx = sc->rge_ldata.rge_rxq_considx = 0;
1179 sc->rge_head = sc->rge_tail = NULL;
1185 rge_rx_list_fini(struct rge_softc *sc)
1191 if (sc->rge_ldata.rge_rxq[i].rxq_mbuf != NULL) {
1192 bus_dmamap_unload(sc->sc_dmat,
1193 sc->rge_ldata.rge_rxq[i].rxq_dmamap);
1194 m_freem(sc->rge_ldata.rge_rxq[i].rxq_mbuf);
1195 sc->rge_ldata.rge_rxq[i].rxq_mbuf = NULL;
1201 rge_tx_list_init(struct rge_softc *sc)
1205 memset(sc->rge_ldata.rge_tx_list, 0, RGE_TX_LIST_SZ);
1208 sc->rge_ldata.rge_txq[i].txq_mbuf = NULL;
1210 bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map, 0,
1211 sc->rge_ldata.rge_tx_list_map->dm_mapsize,
1214 sc->rge_ldata.rge_txq_prodidx = sc->rge_ldata.rge_txq_considx = 0;
1218 rge_tx_list_fini(struct rge_softc *sc)
1224 if (sc->rge_ldata.rge_txq[i].txq_mbuf != NULL) {
1225 bus_dmamap_unload(sc->sc_dmat,
1226 sc->rge_ldata.rge_txq[i].txq_dmamap);
1227 m_freem(sc->rge_ldata.rge_txq[i].txq_mbuf);
1228 sc->rge_ldata.rge_txq[i].txq_mbuf = NULL;
1234 rge_rxeof(struct rge_softc *sc)
1237 struct ifnet *ifp = &sc->sc_ec.ec_if;
1243 for (i = sc->rge_ldata.rge_rxq_considx; ; i = RGE_NEXT_RX_DESC(i)) {
1245 bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_rx_list_map,
1249 cur_rx = &sc->rge_ldata.rge_rx_list[i];
1258 rxq = &sc->rge_ldata.rge_rxq[i];
1263 bus_dmamap_sync(sc->sc_dmat, rxq->rxq_dmamap, 0,
1269 rge_load_rxbuf(sc, i);
1279 if (sc->rge_head != NULL) {
1280 m_freem(sc->rge_head);
1281 sc->rge_head = sc->rge_tail = NULL;
1283 rge_load_rxbuf(sc, i);
1291 if (rge_newbuf(sc, i) != 0) {
1293 if (sc->rge_head != NULL) {
1294 m_freem(sc->rge_head);
1295 sc->rge_head = sc->rge_tail = NULL;
1297 rge_load_rxbuf(sc, i);
1302 if (sc->rge_head != NULL) {
1311 sc->rge_tail->m_len -=
1317 sc->rge_tail->m_next = m;
1319 m = sc->rge_head;
1320 sc->rge_head = sc->rge_tail = NULL;
1357 sc->rge_ldata.rge_rxq_considx = i;
1363 rge_txeof(struct rge_softc *sc)
1365 struct ifnet *ifp = &sc->sc_ec.ec_if;
1371 prod = sc->rge_ldata.rge_txq_prodidx;
1372 cons = sc->rge_ldata.rge_txq_considx;
1375 txq = &sc->rge_ldata.rge_txq[cons];
1378 bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map,
1383 txstat = letoh32(sc->rge_ldata.rge_tx_list[idx].rge_cmdsts);
1390 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 0,
1392 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
1405 bus_dmamap_sync(sc->sc_dmat, sc->rge_ldata.rge_tx_list_map,
1417 sc->rge_ldata.rge_txq_considx = cons;
1420 rge_txstart(sc);
1430 rge_reset(struct rge_softc *sc)
1435 RGE_SETBIT_1(sc, RGE_PPSW, 0x08);
1440 if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY |
1445 if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5) {
1448 if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103)
1456 RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET);
1460 if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET))
1464 device_printf(sc->sc_dev, "reset never completed!\n");
1468 rge_iff(struct rge_softc *sc)
1470 struct ifnet *ifp = &sc->sc_ec.ec_if;
1471 struct ethercom *ec = &sc->sc_ec;
1478 rxfilt = RGE_READ_4(sc, RGE_RXCFG);
1521 RGE_WRITE_4(sc, RGE_RXCFG, rxfilt);
1522 RGE_WRITE_4(sc, RGE_MAR0, bswap32(hashes[1]));
1523 RGE_WRITE_4(sc, RGE_MAR4, bswap32(hashes[0]));
1527 rge_set_phy_power(struct rge_softc *sc, int on)
1532 RGE_SETBIT_1(sc, RGE_PMCH, 0xc0);
1534 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN);
1537 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3)
1542 rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN);
1543 RGE_CLRBIT_1(sc, RGE_PMCH, 0x80);
1544 RGE_CLRBIT_1(sc, RGE_PPSW, 0x40);
1549 rge_phy_config(struct rge_softc *sc)
1552 rge_write_phy_ocp(sc, 0xa436, 0x801e);
1553 sc->rge_mcodever = rge_read_phy_ocp(sc, 0xa438);
1555 switch (sc->rge_type) {
1557 rge_phy_config_mac_cfg2(sc);
1560 rge_phy_config_mac_cfg3(sc);
1563 rge_phy_config_mac_cfg4(sc);
1566 rge_phy_config_mac_cfg5(sc);
1572 rge_write_phy(sc, 0x0a5b, 0x12,
1573 rge_read_phy(sc, 0x0a5b, 0x12) & ~0x8000);
1576 RGE_MAC_CLRBIT(sc, 0xe040, 0x0003);
1577 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
1578 RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006);
1579 RGE_PHY_CLRBIT(sc, 0xa432, 0x0010);
1581 RGE_PHY_CLRBIT(sc, 0xa5d0, 0x0006);
1582 RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001);
1583 RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010);
1584 RGE_PHY_CLRBIT(sc, 0xa428, 0x0080);
1585 RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200);
1587 rge_patch_phy_mcu(sc, 1);
1588 RGE_MAC_CLRBIT(sc, 0xe052, 0x0001);
1589 RGE_PHY_CLRBIT(sc, 0xa442, 0x3000);
1590 RGE_PHY_CLRBIT(sc, 0xa430, 0x8000);
1591 rge_patch_phy_mcu(sc, 0);
1595 rge_phy_config_mac_cfg2(struct rge_softc *sc)
1601 rge_write_ephy(sc, rtl8125_mac_cfg2_ephy[i].reg,
1604 rge_phy_config_mcu(sc, RGE_MAC_CFG2_MCODE_VER);
1606 val = rge_read_phy_ocp(sc, 0xad40) & ~0x03ff;
1607 rge_write_phy_ocp(sc, 0xad40, val | 0x0084);
1608 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
1609 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
1610 rge_write_phy_ocp(sc, 0xad16, val | 0x0006);
1611 val = rge_read_phy_ocp(sc, 0xad32) & ~0x03ff;
1612 rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
1613 RGE_PHY_CLRBIT(sc, 0xac08, 0x1100);
1614 val = rge_read_phy_ocp(sc, 0xac8a) & ~0xf000;
1615 rge_write_phy_ocp(sc, 0xac8a, val | 0x7000);
1616 RGE_PHY_SETBIT(sc, 0xad18, 0x0400);
1617 RGE_PHY_SETBIT(sc, 0xad1a, 0x03ff);
1618 RGE_PHY_SETBIT(sc, 0xad1c, 0x03ff);
1620 rge_write_phy_ocp(sc, 0xa436, 0x80ea);
1621 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1622 rge_write_phy_ocp(sc, 0xa438, val | 0xc400);
1623 rge_write_phy_ocp(sc, 0xa436, 0x80eb);
1624 val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700;
1625 rge_write_phy_ocp(sc, 0xa438, val | 0x0300);
1626 rge_write_phy_ocp(sc, 0xa436, 0x80f8);
1627 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1628 rge_write_phy_ocp(sc, 0xa438, val | 0x1c00);
1629 rge_write_phy_ocp(sc, 0xa436, 0x80f1);
1630 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1631 rge_write_phy_ocp(sc, 0xa438, val | 0x3000);
1632 rge_write_phy_ocp(sc, 0xa436, 0x80fe);
1633 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1634 rge_write_phy_ocp(sc, 0xa438, val | 0xa500);
1635 rge_write_phy_ocp(sc, 0xa436, 0x8102);
1636 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1637 rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
1638 rge_write_phy_ocp(sc, 0xa436, 0x8105);
1639 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1640 rge_write_phy_ocp(sc, 0xa438, val | 0x3300);
1641 rge_write_phy_ocp(sc, 0xa436, 0x8100);
1642 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1643 rge_write_phy_ocp(sc, 0xa438, val | 0x7000);
1644 rge_write_phy_ocp(sc, 0xa436, 0x8104);
1645 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1646 rge_write_phy_ocp(sc, 0xa438, val | 0xf000);
1647 rge_write_phy_ocp(sc, 0xa436, 0x8106);
1648 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1649 rge_write_phy_ocp(sc, 0xa438, val | 0x6500);
1650 rge_write_phy_ocp(sc, 0xa436, 0x80dc);
1651 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1652 rge_write_phy_ocp(sc, 0xa438, val | 0xed00);
1653 rge_write_phy_ocp(sc, 0xa436, 0x80df);
1654 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
1655 rge_write_phy_ocp(sc, 0xa436, 0x80e1);
1656 RGE_PHY_CLRBIT(sc, 0xa438, 0x0100);
1657 val = rge_read_phy_ocp(sc, 0xbf06) & ~0x003f;
1658 rge_write_phy_ocp(sc, 0xbf06, val | 0x0038);
1659 rge_write_phy_ocp(sc, 0xa436, 0x819f);
1660 rge_write_phy_ocp(sc, 0xa438, 0xd0b6);
1661 rge_write_phy_ocp(sc, 0xbc34, 0x5555);
1662 val = rge_read_phy_ocp(sc, 0xbf0a) & ~0x0e00;
1663 rge_write_phy_ocp(sc, 0xbf0a, val | 0x0a00);
1664 RGE_PHY_CLRBIT(sc, 0xa5c0, 0x0400);
1665 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1669 rge_phy_config_mac_cfg3(struct rge_softc *sc)
1671 struct ifnet *ifp = &sc->sc_ec.ec_if;
1687 rge_write_ephy(sc, rtl8125_mac_cfg3_ephy[i].reg,
1690 val = rge_read_ephy(sc, 0x002a) & ~0x7000;
1691 rge_write_ephy(sc, 0x002a, val | 0x3000);
1692 RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040);
1693 RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00);
1694 RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000);
1695 rge_write_ephy(sc, 0x0002, 0x6042);
1696 rge_write_ephy(sc, 0x0006, 0x0014);
1697 val = rge_read_ephy(sc, 0x006a) & ~0x7000;
1698 rge_write_ephy(sc, 0x006a, val | 0x3000);
1699 RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040);
1700 RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00);
1701 RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000);
1702 rge_write_ephy(sc, 0x0042, 0x6042);
1703 rge_write_ephy(sc, 0x0046, 0x0014);
1705 rge_phy_config_mcu(sc, RGE_MAC_CFG3_MCODE_VER);
1707 RGE_PHY_SETBIT(sc, 0xad4e, 0x0010);
1708 val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff;
1709 rge_write_phy_ocp(sc, 0xad16, val | 0x03ff);
1710 val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f;
1711 rge_write_phy_ocp(sc, 0xad32, val | 0x0006);
1712 RGE_PHY_CLRBIT(sc, 0xac08, 0x1000);
1713 RGE_PHY_CLRBIT(sc, 0xac08, 0x0100);
1714 val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003;
1715 rge_write_phy_ocp(sc, 0xacc0, val | 0x0002);
1716 val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0;
1717 rge_write_phy_ocp(sc, 0xad40, val | 0x0040);
1718 val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007;
1719 rge_write_phy_ocp(sc, 0xad40, val | 0x0004);
1720 RGE_PHY_CLRBIT(sc, 0xac14, 0x0080);
1721 RGE_PHY_CLRBIT(sc, 0xac80, 0x0300);
1722 val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007;
1723 rge_write_phy_ocp(sc, 0xac5e, val | 0x0002);
1724 rge_write_phy_ocp(sc, 0xad4c, 0x00a8);
1725 rge_write_phy_ocp(sc, 0xac5c, 0x01ff);
1726 val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0;
1727 rge_write_phy_ocp(sc, 0xac8a, val | 0x0030);
1728 rge_write_phy_ocp(sc, 0xb87c, 0x8157);
1729 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1730 rge_write_phy_ocp(sc, 0xb87e, val | 0x0500);
1731 rge_write_phy_ocp(sc, 0xb87c, 0x8159);
1732 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1733 rge_write_phy_ocp(sc, 0xb87e, val | 0x0700);
1734 RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, ifp->if_mtu + ETHER_HDR_LEN +
1736 rge_write_phy_ocp(sc, 0xb87c, 0x80a2);
1737 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
1738 rge_write_phy_ocp(sc, 0xb87c, 0x809c);
1739 rge_write_phy_ocp(sc, 0xb87e, 0x0153);
1741 rge_write_phy_ocp(sc, 0xa436, 0x81b3);
1743 rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]);
1745 rge_write_phy_ocp(sc, 0xa438, 0);
1746 rge_write_phy_ocp(sc, 0xa436, 0x8257);
1747 rge_write_phy_ocp(sc, 0xa438, 0x020f);
1748 rge_write_phy_ocp(sc, 0xa436, 0x80ea);
1749 rge_write_phy_ocp(sc, 0xa438, 0x7843);
1751 rge_patch_phy_mcu(sc, 1);
1752 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
1753 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
1755 rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]);
1756 rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]);
1758 RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
1759 rge_patch_phy_mcu(sc, 0);
1761 RGE_PHY_SETBIT(sc, 0xd068, 0x2000);
1762 rge_write_phy_ocp(sc, 0xa436, 0x81a2);
1763 RGE_PHY_SETBIT(sc, 0xa438, 0x0100);
1764 val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00;
1765 rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00);
1766 RGE_PHY_CLRBIT(sc, 0xa454, 0x0001);
1767 RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020);
1768 RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010);
1769 RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001);
1770 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1774 rge_phy_config_mac_cfg4(struct rge_softc *sc)
1776 struct ifnet *ifp = &sc->sc_ec.ec_if;
1788 rge_write_ephy(sc, rtl8125_mac_cfg4_ephy[i].reg,
1791 rge_write_phy_ocp(sc, 0xbf86, 0x9000);
1792 RGE_PHY_SETBIT(sc, 0xc402, 0x0400);
1793 RGE_PHY_CLRBIT(sc, 0xc402, 0x0400);
1794 rge_write_phy_ocp(sc, 0xbd86, 0x1010);
1795 rge_write_phy_ocp(sc, 0xbd88, 0x1010);
1796 val = rge_read_phy_ocp(sc, 0xbd4e) & ~0x0c00;
1797 rge_write_phy_ocp(sc, 0xbd4e, val | 0x0800);
1798 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
1799 rge_write_phy_ocp(sc, 0xbf46, val | 0x0700);
1801 rge_phy_config_mcu(sc, RGE_MAC_CFG4_MCODE_VER);
1803 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1804 RGE_PHY_SETBIT(sc, 0xbc08, 0x000c);
1805 rge_write_phy_ocp(sc, 0xa436, 0x8fff);
1806 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1807 rge_write_phy_ocp(sc, 0xa438, val | 0x0400);
1809 rge_write_phy_ocp(sc, 0xb87c, 0x8560 + i * 2);
1811 rge_write_phy_ocp(sc, 0xb87e, 0x19cc);
1813 rge_write_phy_ocp(sc, 0xb87e, 0x147d);
1815 rge_write_phy_ocp(sc, 0xb87c, 0x8ffe);
1816 rge_write_phy_ocp(sc, 0xb87e, 0x0907);
1817 val = rge_read_phy_ocp(sc, 0xacda) & ~0xff00;
1818 rge_write_phy_ocp(sc, 0xacda, val | 0xff00);
1819 val = rge_read_phy_ocp(sc, 0xacde) & ~0xf000;
1820 rge_write_phy_ocp(sc, 0xacde, val | 0xf000);
1821 rge_write_phy_ocp(sc, 0xb87c, 0x80d6);
1822 rge_write_phy_ocp(sc, 0xb87e, 0x2801);
1823 rge_write_phy_ocp(sc, 0xb87c, 0x80F2);
1824 rge_write_phy_ocp(sc, 0xb87e, 0x2801);
1825 rge_write_phy_ocp(sc, 0xb87c, 0x80f4);
1826 rge_write_phy_ocp(sc, 0xb87e, 0x6077);
1827 rge_write_phy_ocp(sc, 0xb506, 0x01e7);
1828 rge_write_phy_ocp(sc, 0xac8c, 0x0ffc);
1829 rge_write_phy_ocp(sc, 0xac46, 0xb7b4);
1830 rge_write_phy_ocp(sc, 0xac50, 0x0fbc);
1831 rge_write_phy_ocp(sc, 0xac3c, 0x9240);
1832 rge_write_phy_ocp(sc, 0xac4E, 0x0db4);
1833 rge_write_phy_ocp(sc, 0xacc6, 0x0707);
1834 rge_write_phy_ocp(sc, 0xacc8, 0xa0d3);
1835 rge_write_phy_ocp(sc, 0xad08, 0x0007);
1837 rge_write_phy_ocp(sc, 0xb87c, mac_cfg4_b87c_value[i]);
1838 rge_write_phy_ocp(sc, 0xb87e, mac_cfg4_b87c_value[i + 1]);
1840 RGE_PHY_SETBIT(sc, 0xbf4c, 0x0002);
1841 RGE_PHY_SETBIT(sc, 0xbcca, 0x0300);
1842 rge_write_phy_ocp(sc, 0xb87c, 0x8141);
1843 rge_write_phy_ocp(sc, 0xb87e, 0x320e);
1844 rge_write_phy_ocp(sc, 0xb87c, 0x8153);
1845 rge_write_phy_ocp(sc, 0xb87e, 0x720e);
1846 RGE_PHY_CLRBIT(sc, 0xa432, 0x0040);
1847 rge_write_phy_ocp(sc, 0xb87c, 0x8529);
1848 rge_write_phy_ocp(sc, 0xb87e, 0x050e);
1849 RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, ifp->if_mtu + ETHER_HDR_LEN +
1851 rge_write_phy_ocp(sc, 0xa436, 0x816c);
1852 rge_write_phy_ocp(sc, 0xa438, 0xc4a0);
1853 rge_write_phy_ocp(sc, 0xa436, 0x8170);
1854 rge_write_phy_ocp(sc, 0xa438, 0xc4a0);
1855 rge_write_phy_ocp(sc, 0xa436, 0x8174);
1856 rge_write_phy_ocp(sc, 0xa438, 0x04a0);
1857 rge_write_phy_ocp(sc, 0xa436, 0x8178);
1858 rge_write_phy_ocp(sc, 0xa438, 0x04a0);
1859 rge_write_phy_ocp(sc, 0xa436, 0x817c);
1860 rge_write_phy_ocp(sc, 0xa438, 0x0719);
1861 rge_write_phy_ocp(sc, 0xa436, 0x8ff4);
1862 rge_write_phy_ocp(sc, 0xa438, 0x0400);
1863 rge_write_phy_ocp(sc, 0xa436, 0x8ff1);
1864 rge_write_phy_ocp(sc, 0xa438, 0x0404);
1865 rge_write_phy_ocp(sc, 0xbf4a, 0x001b);
1867 rge_write_phy_ocp(sc, 0xb87c, 0x8033 + i * 4);
1869 rge_write_phy_ocp(sc, 0xb87e, 0xfc32);
1871 rge_write_phy_ocp(sc, 0xb87e, 0x7c13);
1873 rge_write_phy_ocp(sc, 0xb87c, 0x8145);
1874 rge_write_phy_ocp(sc, 0xb87e, 0x370e);
1875 rge_write_phy_ocp(sc, 0xb87c, 0x8157);
1876 rge_write_phy_ocp(sc, 0xb87e, 0x770e);
1877 rge_write_phy_ocp(sc, 0xb87c, 0x8169);
1878 rge_write_phy_ocp(sc, 0xb87e, 0x0d0a);
1879 rge_write_phy_ocp(sc, 0xb87c, 0x817b);
1880 rge_write_phy_ocp(sc, 0xb87e, 0x1d0a);
1881 rge_write_phy_ocp(sc, 0xa436, 0x8217);
1882 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1883 rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
1884 rge_write_phy_ocp(sc, 0xa436, 0x821a);
1885 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1886 rge_write_phy_ocp(sc, 0xa438, val | 0x5000);
1887 rge_write_phy_ocp(sc, 0xa436, 0x80da);
1888 rge_write_phy_ocp(sc, 0xa438, 0x0403);
1889 rge_write_phy_ocp(sc, 0xa436, 0x80dc);
1890 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1891 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
1892 rge_write_phy_ocp(sc, 0xa436, 0x80b3);
1893 rge_write_phy_ocp(sc, 0xa438, 0x0384);
1894 rge_write_phy_ocp(sc, 0xa436, 0x80b7);
1895 rge_write_phy_ocp(sc, 0xa438, 0x2007);
1896 rge_write_phy_ocp(sc, 0xa436, 0x80ba);
1897 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1898 rge_write_phy_ocp(sc, 0xa438, val | 0x6c00);
1899 rge_write_phy_ocp(sc, 0xa436, 0x80b5);
1900 rge_write_phy_ocp(sc, 0xa438, 0xf009);
1901 rge_write_phy_ocp(sc, 0xa436, 0x80bd);
1902 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1903 rge_write_phy_ocp(sc, 0xa438, val | 0x9f00);
1904 rge_write_phy_ocp(sc, 0xa436, 0x80c7);
1905 rge_write_phy_ocp(sc, 0xa438, 0xf083);
1906 rge_write_phy_ocp(sc, 0xa436, 0x80dd);
1907 rge_write_phy_ocp(sc, 0xa438, 0x03f0);
1908 rge_write_phy_ocp(sc, 0xa436, 0x80df);
1909 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1910 rge_write_phy_ocp(sc, 0xa438, val | 0x1000);
1911 rge_write_phy_ocp(sc, 0xa436, 0x80cb);
1912 rge_write_phy_ocp(sc, 0xa438, 0x2007);
1913 rge_write_phy_ocp(sc, 0xa436, 0x80ce);
1914 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1915 rge_write_phy_ocp(sc, 0xa438, val | 0x6c00);
1916 rge_write_phy_ocp(sc, 0xa436, 0x80c9);
1917 rge_write_phy_ocp(sc, 0xa438, 0x8009);
1918 rge_write_phy_ocp(sc, 0xa436, 0x80d1);
1919 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1920 rge_write_phy_ocp(sc, 0xa438, val | 0x8000);
1921 rge_write_phy_ocp(sc, 0xa436, 0x80a3);
1922 rge_write_phy_ocp(sc, 0xa438, 0x200a);
1923 rge_write_phy_ocp(sc, 0xa436, 0x80a5);
1924 rge_write_phy_ocp(sc, 0xa438, 0xf0ad);
1925 rge_write_phy_ocp(sc, 0xa436, 0x809f);
1926 rge_write_phy_ocp(sc, 0xa438, 0x6073);
1927 rge_write_phy_ocp(sc, 0xa436, 0x80a1);
1928 rge_write_phy_ocp(sc, 0xa438, 0x000b);
1929 rge_write_phy_ocp(sc, 0xa436, 0x80a9);
1930 val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00;
1931 rge_write_phy_ocp(sc, 0xa438, val | 0xc000);
1932 rge_patch_phy_mcu(sc, 1);
1933 RGE_PHY_CLRBIT(sc, 0xb896, 0x0001);
1934 RGE_PHY_CLRBIT(sc, 0xb892, 0xff00);
1935 rge_write_phy_ocp(sc, 0xb88e, 0xc23e);
1936 rge_write_phy_ocp(sc, 0xb890, 0x0000);
1937 rge_write_phy_ocp(sc, 0xb88e, 0xc240);
1938 rge_write_phy_ocp(sc, 0xb890, 0x0103);
1939 rge_write_phy_ocp(sc, 0xb88e, 0xc242);
1940 rge_write_phy_ocp(sc, 0xb890, 0x0507);
1941 rge_write_phy_ocp(sc, 0xb88e, 0xc244);
1942 rge_write_phy_ocp(sc, 0xb890, 0x090b);
1943 rge_write_phy_ocp(sc, 0xb88e, 0xc246);
1944 rge_write_phy_ocp(sc, 0xb890, 0x0c0e);
1945 rge_write_phy_ocp(sc, 0xb88e, 0xc248);
1946 rge_write_phy_ocp(sc, 0xb890, 0x1012);
1947 rge_write_phy_ocp(sc, 0xb88e, 0xc24a);
1948 rge_write_phy_ocp(sc, 0xb890, 0x1416);
1949 RGE_PHY_SETBIT(sc, 0xb896, 0x0001);
1950 rge_patch_phy_mcu(sc, 0);
1951 RGE_PHY_SETBIT(sc, 0xa86a, 0x0001);
1952 RGE_PHY_SETBIT(sc, 0xa6f0, 0x0001);
1953 rge_write_phy_ocp(sc, 0xbfa0, 0xd70d);
1954 rge_write_phy_ocp(sc, 0xbfa2, 0x4100);
1955 rge_write_phy_ocp(sc, 0xbfa4, 0xe868);
1956 rge_write_phy_ocp(sc, 0xbfa6, 0xdc59);
1957 rge_write_phy_ocp(sc, 0xb54c, 0x3c18);
1958 RGE_PHY_CLRBIT(sc, 0xbfa4, 0x0020);
1959 rge_write_phy_ocp(sc, 0xa436, 0x817d);
1960 RGE_PHY_SETBIT(sc, 0xa438, 0x1000);
1964 rge_phy_config_mac_cfg5(struct rge_softc *sc)
1966 struct ifnet *ifp = &sc->sc_ec.ec_if;
1971 rge_write_ephy(sc, rtl8125_mac_cfg5_ephy[i].reg,
1974 val = rge_read_ephy(sc, 0x0022) & ~0x0030;
1975 rge_write_ephy(sc, 0x0022, val | 0x0020);
1976 val = rge_read_ephy(sc, 0x0062) & ~0x0030;
1977 rge_write_ephy(sc, 0x0062, val | 0x0020);
1979 rge_phy_config_mcu(sc, RGE_MAC_CFG5_MCODE_VER);
1981 RGE_PHY_SETBIT(sc, 0xa442, 0x0800);
1982 val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0;
1983 rge_write_phy_ocp(sc, 0xac46, val | 0x0090);
1984 val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003;
1985 rge_write_phy_ocp(sc, 0xad30, val | 0x0001);
1986 RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, ifp->if_mtu + ETHER_HDR_LEN +
1988 rge_write_phy_ocp(sc, 0xb87c, 0x80f5);
1989 rge_write_phy_ocp(sc, 0xb87e, 0x760e);
1990 rge_write_phy_ocp(sc, 0xb87c, 0x8107);
1991 rge_write_phy_ocp(sc, 0xb87e, 0x360e);
1992 rge_write_phy_ocp(sc, 0xb87c, 0x8551);
1993 val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00;
1994 rge_write_phy_ocp(sc, 0xb87e, val | 0x0800);
1995 val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000;
1996 rge_write_phy_ocp(sc, 0xbf00, val | 0xa000);
1997 val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00;
1998 rge_write_phy_ocp(sc, 0xbf46, val | 0x0300);
2000 rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6);
2001 rge_write_phy_ocp(sc, 0xa438, 0x2417);
2003 RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040);
2004 val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000;
2005 rge_write_phy_ocp(sc, 0xbf84, val | 0xa000);
2009 rge_phy_config_mcu(struct rge_softc *sc, uint16_t mcode_version)
2011 if (sc->rge_mcodever != mcode_version) {
2014 rge_patch_phy_mcu(sc, 1);
2016 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
2017 rge_write_phy_ocp(sc, 0xa436, 0x8024);
2018 if (sc->rge_type == MAC_CFG2)
2019 rge_write_phy_ocp(sc, 0xa438, 0x8600);
2021 rge_write_phy_ocp(sc, 0xa438, 0x8601);
2022 rge_write_phy_ocp(sc, 0xa436, 0xb82e);
2023 rge_write_phy_ocp(sc, 0xa438, 0x0001);
2025 RGE_PHY_SETBIT(sc, 0xb820, 0x0080);
2028 if (sc->rge_type == MAC_CFG2) {
2030 rge_write_phy_ocp(sc,
2034 } else if (sc->rge_type == MAC_CFG3) {
2036 rge_write_phy_ocp(sc,
2040 } else if (sc->rge_type == MAC_CFG4) {
2042 rge_write_phy_ocp(sc,
2046 } else if (sc->rge_type == MAC_CFG5) {
2048 rge_write_phy_ocp(sc,
2054 if (sc->rge_type == MAC_CFG2 || sc->rge_type == MAC_CFG3) {
2055 RGE_PHY_CLRBIT(sc, 0xb820, 0x0080);
2057 rge_write_phy_ocp(sc, 0xa436, 0);
2058 rge_write_phy_ocp(sc, 0xa438, 0);
2059 RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001);
2060 rge_write_phy_ocp(sc, 0xa436, 0x8024);
2061 rge_write_phy_ocp(sc, 0xa438, 0);
2064 rge_patch_phy_mcu(sc, 0);
2067 rge_write_phy_ocp(sc, 0xa436, 0x801e);
2068 rge_write_phy_ocp(sc, 0xa438, mcode_version);
2073 rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr)
2075 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2076 RGE_WRITE_4(sc, RGE_MAC0,
2078 RGE_WRITE_4(sc, RGE_MAC4,
2080 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2084 rge_get_macaddr(struct rge_softc *sc, uint8_t *addr)
2089 addr[i] = RGE_READ_1(sc, RGE_ADDR0 + i);
2093 rge_hw_init(struct rge_softc *sc)
2097 RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2098 RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS);
2099 RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN);
2100 RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG);
2101 RGE_CLRBIT_1(sc, 0xf1, 0x80);
2104 RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010);
2107 rge_write_mac_ocp(sc, 0xfc38, 0);
2110 rge_write_mac_ocp(sc, i, 0);
2113 rge_write_mac_ocp(sc, 0xfc26, 0);
2115 if (sc->rge_type == MAC_CFG3) {
2117 rge_write_mac_ocp(sc, rtl8125_mac_bps[i].reg,
2120 } else if (sc->rge_type == MAC_CFG5) {
2122 rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg,
2128 rge_disable_phy_ocp_pwrsave(sc);
2131 rge_write_csi(sc, 0x108,
2132 rge_read_csi(sc, 0x108) | 0x00100000);
2136 rge_disable_phy_ocp_pwrsave(struct rge_softc *sc)
2138 if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) {
2139 rge_patch_phy_mcu(sc, 1);
2140 rge_write_phy_ocp(sc, 0xc416, 0);
2141 rge_write_phy_ocp(sc, 0xc416, 0x0500);
2142 rge_patch_phy_mcu(sc, 0);
2147 rge_patch_phy_mcu(struct rge_softc *sc, int set)
2152 RGE_PHY_SETBIT(sc, 0xb820, 0x0010);
2154 RGE_PHY_CLRBIT(sc, 0xb820, 0x0010);
2157 if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) == 0x0040)
2168 rge_add_media_types(struct rge_softc *sc)
2170 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL);
2171 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
2172 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL);
2173 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
2174 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T, 0, NULL);
2175 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2176 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL);
2177 ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL);
2181 rge_config_imtype(struct rge_softc *sc, int imtype)
2185 sc->rge_intrs = RGE_INTRS;
2186 sc->rge_rx_ack = RGE_ISR_RX_OK | RGE_ISR_RX_DESC_UNAVAIL |
2188 sc->rge_tx_ack = RGE_ISR_TX_OK;
2191 sc->rge_intrs = RGE_INTRS_TIMER;
2192 sc->rge_rx_ack = RGE_ISR_PCS_TIMEOUT;
2193 sc->rge_tx_ack = RGE_ISR_PCS_TIMEOUT;
2196 panic("%s: unknown imtype %d", device_xname(sc->sc_dev), imtype);
2201 rge_disable_hw_im(struct rge_softc *sc)
2203 RGE_WRITE_2(sc, RGE_IM, 0);
2207 rge_disable_sim_im(struct rge_softc *sc)
2209 RGE_WRITE_4(sc, RGE_TIMERINT0, 0);
2210 sc->rge_timerintr = 0;
2214 rge_setup_sim_im(struct rge_softc *sc)
2216 RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600);
2217 RGE_WRITE_4(sc, RGE_TIMERCNT, 1);
2218 sc->rge_timerintr = 1;
2222 rge_setup_intr(struct rge_softc *sc, int imtype)
2224 rge_config_imtype(sc, imtype);
2227 RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs);
2231 rge_disable_sim_im(sc);
2232 rge_disable_hw_im(sc);
2235 rge_disable_hw_im(sc);
2236 rge_setup_sim_im(sc);
2239 panic("%s: unknown imtype %d", device_xname(sc->sc_dev), imtype);
2244 rge_exit_oob(struct rge_softc *sc)
2248 RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV |
2253 rge_write_mac_ocp(sc, 0xc0bc, 0x00ff);
2255 rge_reset(sc);
2258 RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB);
2260 RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000);
2264 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
2268 rge_write_mac_ocp(sc, 0xc0aa, 0x07d0);
2269 rge_write_mac_ocp(sc, 0xc0a6, 0x01b5);
2270 rge_write_mac_ocp(sc, 0xc01e, 0x5555);
2274 if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200)
2278 if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) {
2280 device_xname(sc->sc_dev));
2282 if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2)
2286 RGE_MAC_CLRBIT(sc, 0xd408, 0x0100);
2287 if (sc->rge_type == MAC_CFG4 || sc->rge_type == MAC_CFG5)
2288 RGE_PHY_CLRBIT(sc, 0xa466, 0x0001);
2289 RGE_PHY_CLRBIT(sc, 0xa468, 0x000a);
2294 rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val)
2298 RGE_WRITE_4(sc, RGE_CSIDR, val);
2299 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
2304 if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY))
2312 rge_read_csi(struct rge_softc *sc, uint32_t reg)
2316 RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) |
2321 if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)
2327 return (RGE_READ_4(sc, RGE_CSIDR));
2331 rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
2338 RGE_WRITE_4(sc, RGE_MACOCP, tmp);
2342 rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg)
2347 RGE_WRITE_4(sc, RGE_MACOCP, val);
2349 return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK);
2353 rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val)
2360 RGE_WRITE_4(sc, RGE_EPHYAR, tmp);
2364 if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY))
2372 rge_read_ephy(struct rge_softc *sc, uint16_t reg)
2378 RGE_WRITE_4(sc, RGE_EPHYAR, val);
2382 val = RGE_READ_4(sc, RGE_EPHYAR);
2393 rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val)
2404 rge_write_phy_ocp(sc, phyaddr, val);
2408 rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg)
2419 return (rge_read_phy_ocp(sc, phyaddr));
2423 rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val)
2430 RGE_WRITE_4(sc, RGE_PHYOCP, tmp);
2434 if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY))
2440 rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg)
2446 RGE_WRITE_4(sc, RGE_PHYOCP, val);
2450 val = RGE_READ_4(sc, RGE_PHYOCP);
2459 rge_get_link_status(struct rge_softc *sc)
2461 return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0);
2467 struct rge_softc *sc = arg;
2469 RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START);
2475 struct rge_softc *sc = arg;
2479 rge_link_state(sc);
2482 callout_schedule(&sc->sc_timeout, hz);
2486 rge_link_state(struct rge_softc *sc)
2488 struct ifnet *ifp = &sc->sc_ec.ec_if;
2491 if (rge_get_link_status(sc))