Lines Matching refs:IWM_SCD_BASE
1189 #define IWM_SCD_BASE (IWM_PRPH_BASE + 0xa02c00) macro
1191 #define IWM_SCD_SRAM_BASE_ADDR (IWM_SCD_BASE + 0x0)
1192 #define IWM_SCD_DRAM_BASE_ADDR (IWM_SCD_BASE + 0x8)
1193 #define IWM_SCD_AIT (IWM_SCD_BASE + 0x0c)
1194 #define IWM_SCD_TXFACT (IWM_SCD_BASE + 0x10)
1195 #define IWM_SCD_ACTIVE (IWM_SCD_BASE + 0x14)
1196 #define IWM_SCD_QUEUECHAIN_SEL (IWM_SCD_BASE + 0xe8)
1197 #define IWM_SCD_CHAINEXT_EN (IWM_SCD_BASE + 0x244)
1198 #define IWM_SCD_AGGR_SEL (IWM_SCD_BASE + 0x248)
1199 #define IWM_SCD_INTERRUPT_MASK (IWM_SCD_BASE + 0x108)
1200 #define IWM_SCD_GP_CTRL (IWM_SCD_BASE + 0x1a8)
1201 #define IWM_SCD_EN_CTRL (IWM_SCD_BASE + 0x254)
1206 return IWM_SCD_BASE + 0x18 + chnl * 4; in IWM_SCD_QUEUE_WRPTR()
1207 return IWM_SCD_BASE + 0x284 + (chnl - 20) * 4; in IWM_SCD_QUEUE_WRPTR()
1213 return IWM_SCD_BASE + 0x68 + chnl * 4; in IWM_SCD_QUEUE_RDPTR()
1214 return IWM_SCD_BASE + 0x2B4 + (chnl - 20) * 4; in IWM_SCD_QUEUE_RDPTR()
1220 return IWM_SCD_BASE + 0x10c + chnl * 4; in IWM_SCD_QUEUE_STATUS_BITS()
1221 return IWM_SCD_BASE + 0x384 + (chnl - 20) * 4; in IWM_SCD_QUEUE_STATUS_BITS()