2808 	uint64_t mpi_ctrl;  in fw2x_set_mode()  local
2813 	mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);  in fw2x_set_mode()
2817 		mpi_ctrl &= ~FW2X_CTRL_RATE_MASK;  in fw2x_set_mode()
2819 			mpi_ctrl |= FW2X_CTRL_RATE_10G;  in fw2x_set_mode()
2821 			mpi_ctrl |= FW2X_CTRL_RATE_5G;  in fw2x_set_mode()
2823 			mpi_ctrl |= FW2X_CTRL_RATE_2G5;  in fw2x_set_mode()
2825 			mpi_ctrl |= FW2X_CTRL_RATE_1G;  in fw2x_set_mode()
2827 			mpi_ctrl |= FW2X_CTRL_RATE_100M;  in fw2x_set_mode()
2829 		mpi_ctrl &= ~FW2X_CTRL_LINK_DROP;  in fw2x_set_mode()
2831 		mpi_ctrl &= ~FW2X_CTRL_EEE_MASK;  in fw2x_set_mode()
2833 			mpi_ctrl |= FW2X_CTRL_EEE_MASK;  in fw2x_set_mode()
2835 		mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);  in fw2x_set_mode()
2837 			mpi_ctrl |= FW2X_CTRL_PAUSE;  in fw2x_set_mode()
2839 			mpi_ctrl |= FW2X_CTRL_ASYMMETRIC_PAUSE;  in fw2x_set_mode()
2842 		mpi_ctrl &= ~(FW2X_CTRL_RATE_MASK | FW2X_CTRL_EEE_MASK);  in fw2x_set_mode()
2843 		mpi_ctrl &= ~(FW2X_CTRL_PAUSE | FW2X_CTRL_ASYMMETRIC_PAUSE);  in fw2x_set_mode()
2850 	AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);  in fw2x_set_mode()
2864 		uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);  in fw2x_get_mode()  local
2865 		if (mpi_ctrl & FW2X_CTRL_RATE_MASK)  in fw2x_get_mode()
2905 	uint64_t mpi_ctrl = AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG);  in toggle_mpi_ctrl_and_wait()  local
2910 	if ((mpi_ctrl & mask) != (mpi_state & mask)) {  in toggle_mpi_ctrl_and_wait()
2914 		    (unsigned long long)mpi_ctrl, (unsigned long long)mpi_state,  in toggle_mpi_ctrl_and_wait()
2920 	mpi_ctrl ^= mask;  in toggle_mpi_ctrl_and_wait()
2921 	AQ_WRITE64_REG(sc, FW2X_MPI_CONTROL_REG, mpi_ctrl);  in toggle_mpi_ctrl_and_wait()
2924 	mpi_ctrl &= mask;  in toggle_mpi_ctrl_and_wait()
2927 	WAIT_FOR((AQ_READ64_REG(sc, FW2X_MPI_CONTROL_REG) & mask) == mpi_ctrl,  in toggle_mpi_ctrl_and_wait()