Lines Matching defs:adap
116 * @adap: the adapter
126 static void t3_read_indirect(adapter_t *adap, unsigned int addr_reg,
131 t3_write_reg(adap, addr_reg, start_idx);
132 *vals++ = t3_read_reg(adap, data_reg);
154 adapter_t *adap = mc7->adapter;
168 t3_write_reg(adap, mc7->offset + A_MC7_BD_ADDR,
170 t3_write_reg(adap, mc7->offset + A_MC7_BD_OP, 0);
171 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_OP);
173 val = t3_read_reg(adap,
178 val = t3_read_reg(adap, mc7->offset + A_MC7_BD_DATA1);
180 val64 = t3_read_reg(adap,
198 static void mi1_init(adapter_t *adap, const struct adapter_info *ai)
200 u32 clkdiv = adap->params.vpd.cclk / (2 * adap->params.vpd.mdc) - 1;
206 t3_write_reg(adap, A_MI1_CFG, val);
1075 * @adap: the adapter
1082 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
1087 if (t3_read_reg(adap, A_CIM_HOST_ACC_CTRL) & F_HOSTBUSY)
1091 t3_write_reg(adap, A_CIM_HOST_ACC_CTRL, CIM_CTL_BASE + addr);
1092 ret = t3_wait_op_done(adap, A_CIM_HOST_ACC_CTRL, F_HOSTBUSY,
1095 *valp++ = t3_read_reg(adap, A_CIM_HOST_ACC_DATA);
1587 static int mac_intr_handler(adapter_t *adap, unsigned int idx)
1592 idx = idx == 0 ? 0 : adapter_info(adap)->nports0; /* MAC idx -> port */
1593 mac = &adap2pinfo(adap, idx)->mac;
1594 cause = t3_read_reg(adap, A_XGM_INT_CAUSE + mac->offset);
1598 CH_ALERT(adap, "port%d: MAC TX FIFO parity error\n", idx);
1602 CH_ALERT(adap, "port%d: MAC RX FIFO parity error\n", idx);
1615 t3_write_reg(adap, A_XGM_INT_CAUSE + mac->offset, cause);
1617 t3_fatal_err(adap);
2363 * @adap: the adapter
2368 void t3_tp_set_offload_mode(adapter_t *adap, int enable)
2370 if (is_offload(adap) || !enable)
2371 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE,
2377 * @adap: the adapter
2384 static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
2387 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2388 val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
2389 t3_write_reg(adap, A_TP_PIO_DATA, val);
2394 * @adap: the adapter
2398 void t3_enable_filters(adapter_t *adap)
2400 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
2401 t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
2402 t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
2403 tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
2423 #define mem_region(adap, start, size, reg) \
2424 t3_write_reg((adap), A_ ## reg, (start)); \
2461 * @adap: the adapter
2467 static void partition_mem(adapter_t *adap, const struct tp_params *p)
2469 unsigned int m, pstructs, tids = t3_mc5_size(&adap->mc5);
2472 if (adap->params.rev > 0) {
2485 t3_write_reg(adap, A_TP_PMM_SIZE,
2488 t3_write_reg(adap, A_TP_PMM_TX_BASE, 0);
2489 t3_write_reg(adap, A_TP_PMM_TX_PAGE_SIZE, p->tx_pg_size);
2490 t3_write_reg(adap, A_TP_PMM_TX_MAX_PAGE, p->tx_num_pgs);
2491 t3_set_reg_field(adap, A_TP_PARA_REG3, V_TXDATAACKIDX(M_TXDATAACKIDX),
2494 t3_write_reg(adap, A_TP_PMM_RX_BASE, 0);
2495 t3_write_reg(adap, A_TP_PMM_RX_PAGE_SIZE, p->rx_pg_size);
2496 t3_write_reg(adap, A_TP_PMM_RX_MAX_PAGE, p->rx_num_pgs);
2502 t3_write_reg(adap, A_TP_CMM_MM_MAX_PSTRUCT, pstructs);
2505 mem_region(adap, m, (64 << 10) * 64, SG_EGR_CNTX_BADDR);
2506 mem_region(adap, m, (64 << 10) * 64, SG_CQ_CONTEXT_BADDR);
2507 t3_write_reg(adap, A_TP_CMM_TIMER_BASE, V_CMTIMERMAXNUM(timers) | m);
2509 mem_region(adap, m, pstructs * 64, TP_CMM_MM_BASE);
2510 mem_region(adap, m, 64 * (pstructs / 24), TP_CMM_MM_PS_FLST_BASE);
2511 mem_region(adap, m, 64 * (p->rx_num_pgs / 24), TP_CMM_MM_RX_FLST_BASE);
2512 mem_region(adap, m, 64 * (p->tx_num_pgs / 24), TP_CMM_MM_TX_FLST_BASE);
2515 t3_write_reg(adap, A_CIM_SDRAM_BASE_ADDR, m);
2516 t3_write_reg(adap, A_CIM_SDRAM_ADDR_SIZE, p->cm_size - m);
2519 m = t3_mc5_size(&adap->mc5) - adap->params.mc5.nservers -
2520 adap->params.mc5.nfilters - adap->params.mc5.nroutes;
2522 adap->params.mc5.nservers += m - tids;
2525 static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val)
2527 t3_write_reg(adap, A_TP_PIO_ADDR, addr);
2528 t3_write_reg(adap, A_TP_PIO_DATA, val);
2531 static void tp_config(adapter_t *adap, const struct tp_params *p)
2533 t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
2536 t3_write_reg(adap, A_TP_TCP_OPTIONS, V_MTUDEFAULT(576) |
2539 t3_write_reg(adap, A_TP_DACK_CONFIG, V_AUTOSTATE3(1) |
2543 t3_set_reg_field(adap, A_TP_IN_CONFIG, F_IPV6ENABLE | F_NICMODE,
2545 t3_write_reg(adap, A_TP_TX_RESOURCE_LIMIT, 0x18141814);
2546 t3_write_reg(adap, A_TP_PARA_REG4, 0x5050105);
2547 t3_set_reg_field(adap, A_TP_PARA_REG6, 0,
2548 adap->params.rev > 0 ? F_ENABLEESND :
2550 t3_set_reg_field(adap, A_TP_PC_CONFIG,
2554 t3_set_reg_field(adap, A_TP_PC_CONFIG2, F_CHDRAFULL, 0);
2555 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1080);
2556 t3_write_reg(adap, A_TP_PROXY_FLOW_CNTL, 1000);
2558 if (adap->params.rev > 0) {
2559 tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
2560 t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
2562 t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
2563 tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
2564 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
2565 tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
2567 t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
2569 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT1, 0);
2570 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0, 0);
2571 t3_write_reg(adap, A_TP_MOD_CHANNEL_WEIGHT, 0);
2572 t3_write_reg(adap, A_TP_MOD_RATE_LIMIT, 0xf2200000);
2574 if (adap->params.nports > 2) {
2575 t3_set_reg_field(adap, A_TP_PC_CONFIG2, 0,
2577 tp_wr_bits_indirect(adap, A_TP_QOS_RX_MAP_MODE,
2579 tp_wr_indirect(adap, A_TP_INGRESS_CONFIG, V_BITPOS0(48) |
2583 tp_wr_indirect(adap, A_TP_PREAMBLE_MSB, 0xfb000000);
2584 tp_wr_indirect(adap, A_TP_PREAMBLE_LSB, 0xd5);
2585 tp_wr_indirect(adap, A_TP_INTF_FROM_TX_PKT, F_INTFFROMTXPKT);
2595 * @adap: the adapter to set
2601 static void tp_set_timers(adapter_t *adap, unsigned int core_clk)
2603 unsigned int tre = adap->params.tp.tre;
2604 unsigned int dack_re = adap->params.tp.dack_re;
2608 t3_write_reg(adap, A_TP_TIMER_RESOLUTION, V_TIMERRESOLUTION(tre) |
2611 t3_write_reg(adap, A_TP_DACK_TIMER,
2613 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG0, 0x3020100);
2614 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG1, 0x7060504);
2615 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG2, 0xb0a0908);
2616 t3_write_reg(adap, A_TP_TCP_BACKOFF_REG3, 0xf0e0d0c);
2617 t3_write_reg(adap, A_TP_SHIFT_CNT, V_SYNSHIFTMAX(6) |
2624 t3_write_reg(adap, A_TP_MSL,
2625 adap->params.rev > 0 ? 0 : 2 SECONDS);
2626 t3_write_reg(adap, A_TP_RXT_MIN, tps / (1000 / TP_RTO_MIN));
2627 t3_write_reg(adap, A_TP_RXT_MAX, 64 SECONDS);
2628 t3_write_reg(adap, A_TP_PERS_MIN, 5 SECONDS);
2629 t3_write_reg(adap, A_TP_PERS_MAX, 64 SECONDS);
2630 t3_write_reg(adap, A_TP_KEEP_IDLE, 7200 SECONDS);
2631 t3_write_reg(adap, A_TP_KEEP_INTVL, 75 SECONDS);
2632 t3_write_reg(adap, A_TP_INIT_SRTT, 3 SECONDS);
2633 t3_write_reg(adap, A_TP_FINWAIT2_TIMER, 600 SECONDS);
2641 * @adap: the adapter
2647 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh)
2654 val = t3_read_reg(adap, A_TP_PARA_REG3);
2662 t3_write_reg(adap, A_TP_PARA_REG2, V_RXCOALESCESIZE(size) |
2665 t3_write_reg(adap, A_TP_PARA_REG3, val);
2671 * @adap: the adapter
2677 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size)
2679 t3_write_reg(adap, A_TP_PARA_REG7,
2757 * @adap: the adapter
2767 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
2784 t3_write_reg(adap, A_TP_MTU_TABLE,
2793 t3_write_reg(adap, A_TP_CCTRL_TABLE, (i << 21) |
2801 * @adap: the adapter
2806 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS])
2813 t3_write_reg(adap, A_TP_MTU_TABLE, 0xff000000 | i);
2814 val = t3_read_reg(adap, A_TP_MTU_TABLE);
2821 * @adap: the adapter
2827 void t3_get_cong_cntl_tab(adapter_t *adap,
2834 t3_write_reg(adap, A_TP_CCTRL_TABLE,
2836 incr[mtu][w] = (unsigned short)t3_read_reg(adap,
2843 * @adap: the adapter
2848 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps)
2850 t3_read_indirect(adap, A_TP_MIB_INDEX, A_TP_MIB_RDATA, (u32 *)tps,
2856 * @adap: the adapter
2861 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED])
2863 unsigned int i, tick_ns = dack_ticks_to_usec(adap, 1000);
2866 t3_write_reg(adap, A_TP_PACE_TABLE, 0xffff0000 + i);
2867 pace_vals[i] = t3_read_reg(adap, A_TP_PACE_TABLE) * tick_ns;
2873 * @adap: the adapter
2880 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
2883 unsigned int tick_ns = dack_ticks_to_usec(adap, 1000);
2886 t3_write_reg(adap, A_TP_PACE_TABLE, (start << 16) |
2890 #define ulp_region(adap, name, start, len) \
2891 t3_write_reg((adap), A_ULPRX_ ## name ## _LLIMIT, (start)); \
2892 t3_write_reg((adap), A_ULPRX_ ## name ## _ULIMIT, \
2896 #define ulptx_region(adap, name, start, len) \
2897 t3_write_reg((adap), A_ULPTX_ ## name ## _LLIMIT, (start)); \
2898 t3_write_reg((adap), A_ULPTX_ ## name ## _ULIMIT, \
2901 static void ulp_config(adapter_t *adap, const struct tp_params *p)
2905 ulp_region(adap, ISCSI, m, p->chan_rx_size / 8);
2906 ulp_region(adap, TDDP, m, p->chan_rx_size / 8);
2907 ulptx_region(adap, TPT, m, p->chan_rx_size / 4);
2908 ulp_region(adap, STAG, m, p->chan_rx_size / 4);
2909 ulp_region(adap, RQ, m, p->chan_rx_size / 4);
2910 ulptx_region(adap, PBL, m, p->chan_rx_size / 4);
2911 ulp_region(adap, PBL, m, p->chan_rx_size / 4);
2912 t3_write_reg(adap, A_ULPRX_TDDP_TAGMASK, 0xffffffff);
2923 int t3_set_proto_sram(adapter_t *adap, const u8 *data)
2929 t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
2930 t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
2931 t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
2932 t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
2933 t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
2935 t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
2936 if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
2987 * @adap: the adapter
2993 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched)
2996 unsigned int clk = adap->params.vpd.cclk * 1000;
3018 t3_write_reg(adap, A_TP_TM_PIO_ADDR,
3020 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3025 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3031 * @adap: the adapter
3037 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg)
3042 ipg *= core_ticks_per_usec(adap);
3047 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3048 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3053 t3_write_reg(adap, A_TP_TM_PIO_DATA, v);
3054 t3_read_reg(adap, A_TP_TM_PIO_DATA);
3060 * @adap: the adapter
3067 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
3074 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3075 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3083 v = (adap->params.vpd.cclk * 1000) / cpt;
3089 t3_write_reg(adap, A_TP_TM_PIO_ADDR, addr);
3090 v = t3_read_reg(adap, A_TP_TM_PIO_DATA);
3094 *ipg = (10000 * v) / core_ticks_per_usec(adap);
3100 * @adap: the adapter
3105 static int tp_init(adapter_t *adap, const struct tp_params *p)
3109 tp_config(adap, p);
3110 t3_set_vlan_accel(adap, 3, 0);
3112 if (is_offload(adap)) {
3113 tp_set_timers(adap, adap->params.vpd.cclk * 1000);
3114 t3_write_reg(adap, A_TP_RESET, F_FLSTINITENABLE);
3115 busy = t3_wait_op_done(adap, A_TP_RESET, F_FLSTINITENABLE,
3118 CH_ERR(adap, "TP initialization timed out\n");
3122 t3_write_reg(adap, A_TP_RESET, F_TPRESET);
3128 * @adap: the adapter
3133 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask)
3135 if (port_mask & ~((1 << adap->params.nports) - 1))
3137 t3_set_reg_field(adap, A_MPS_CFG, F_PORT1ACTIVE | F_PORT0ACTIVE,
3144 * @adap: the adapter
3150 static void chan_init_hw(adapter_t *adap, unsigned int chan_map)
3155 t3_set_reg_field(adap, A_ULPRX_CTL, F_ROUND_ROBIN, 0);
3156 t3_set_reg_field(adap, A_ULPTX_CONFIG, F_CFG_RR_ARB, 0);
3157 t3_write_reg(adap, A_MPS_CFG, F_TPRXPORTEN | F_ENFORCEPKT |
3160 t3_write_reg(adap, A_PM1_TX_CFG,
3163 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3165 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xd9c8);
3166 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfbea);
3168 t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
3169 t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
3170 t3_write_reg(adap, A_ULPTX_DMA_WEIGHT,
3172 t3_write_reg(adap, A_MPS_CFG, F_TPTXPORT0EN | F_TPTXPORT1EN |
3175 t3_write_reg(adap, A_PM1_TX_CFG, 0x80008000);
3176 t3_set_reg_field(adap, A_TP_PC_CONFIG, 0, F_TXTOSQUEUEMAPMODE);
3177 t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
3180 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
3182 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xba98);
3183 t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfedc);
3369 static void config_pcie(adapter_t *adap)
3388 t3_os_pci_read_config_2(adap,
3389 adap->params.pci.pcie_cap_addr + PCI_EXP_DEVCTL,
3393 t3_os_pci_read_config_2(adap,
3394 adap->params.pci.pcie_cap_addr + PCI_EXP_LNKCTL,
3397 fst_trn_tx = G_NUMFSTTRNSEQ(t3_read_reg(adap, A_PCIE_PEX_CTRL0));
3398 fst_trn_rx = adap->params.rev == 0 ? fst_trn_tx :
3399 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3400 log2_width = fls(adap->params.pci.width) - 1;
3406 if (adap->params.rev == 0)
3407 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1,
3411 t3_set_reg_field(adap, A_PCIE_PEX_CTRL1, V_ACKLAT(M_ACKLAT),
3414 t3_set_reg_field(adap, A_PCIE_PEX_CTRL0, V_REPLAYLMT(M_REPLAYLMT),
3417 t3_write_reg(adap, A_PCIE_PEX_ERR, 0xffffffff);
3418 t3_set_reg_field(adap, A_PCIE_CFG, F_PCIE_CLIDECEN, F_PCIE_CLIDECEN);