42 #define GTPCI_CS0BARS(p)	(0x0c08 | ((p) << 7))	/*   CSn[0] */  argument
43 #define GTPCI_CS1BARS(p)	(0x0d08 | ((p) << 7))	/*   CSn[1] */  argument
44 #define GTPCI_CS2BARS(p)	(0x0c0c | ((p) << 7))	/*   CSn[2] */  argument
45 #define GTPCI_CS3BARS(p)	(0x0d0c | ((p) << 7))	/*   CSn[3] */  argument
46 #define GTPCI_DCS0BARS(p)	(0x0c10 | ((p) << 7))	/*   DevCSn[0] */  argument
47 #define GTPCI_DCS1BARS(p)	(0x0d10 | ((p) << 7))	/*   DevCSn[1] */  argument
48 #define GTPCI_DCS2BARS(p)	(0x0d18 | ((p) << 7))	/*   DevCSn[2] */  argument
49 #define GTPCI_BCSBARS(p)	(0x0d14 | ((p) << 7))	/*   Boot CSn */  argument
50 #define GTPCI_P2PM0BARS(p)	(0x0d1c	| ((p) << 7))	/*   P2P Mem0 */  argument
51 #define GTPCI_P2PIOBARS(p)	(0x0d24 | ((p) << 7))	/*   P2P I/O */  argument
52 #define GTPCI_EROMBARS(p)	(0x0d2c | ((p) << 7))	/*   Expansion ROM */  argument
54 #define GTPCI_BARE(p)		(0x0c3c | ((p) << 7))	/* Base Addr Reg En */  argument
70 #define GTPCI_CS0BAR(p)		(0x0c48 | ((p) << 7))	/*   CSn[0] */  argument
71 #define GTPCI_CS1BAR(p)		(0x0d48 | ((p) << 7))	/*   CSn[1] */  argument
72 #define GTPCI_CS2BAR(p)		(0x0c4c | ((p) << 7))	/*   CSn[2] */  argument
73 #define GTPCI_CS3BAR(p)		(0x0d4c | ((p) << 7))	/*   CSn[3] */  argument
74 #define GTPCI_DCS0BAR(p)	(0x0c50 | ((p) << 7))	/*   DevCSn[0] */  argument
75 #define GTPCI_DCS1BAR(p)	(0x0d50 | ((p) << 7))	/*   DevCSn[1] */  argument
76 #define GTPCI_DCS2BAR(p)	(0x0d58 | ((p) << 7))	/*   DevCSn[2] */  argument
77 #define GTPCI_BCSBAR(p)		(0x0d54 | ((p) << 7))	/*   Boot CSn */  argument
78 #define GTPCI_P2PM0BARL(p)	(0x0d5c | ((p) << 7))	/*   P2P Mem0 (Low) */  argument
79 #define GTPCI_P2PM0BARH(p)	(0x0d60 | ((p) << 7))	/*   P2P Mem0 (High) */  argument
80 #define GTPCI_P2PIOBAR(p)	(0x0d6c | ((p) << 7))	/*   P2P I/O */  argument
81 #define GTPCI_EROMBAR(p)	(0x0f38 | ((p) << 7))	/*   Expression ROM */  argument
82 #define GTPCI_DRAMBARBS(p)	(0x0c1c | ((p) << 7))	/*DRAM BAR Bank Select*/  argument
83 #define GTPCI_ADC(p)		(0x0d3c | ((p) << 7))	/* Addr Decode Ctrl */  argument
87 #define GTPCI_DLLC(p)		(0x1d20 | ((p) << 7))	/* PCI DLL Control */  argument
88 #define GTPCI_MPPPC(p)		(0x1d1c | ((p) << 7))	/*PCI/MPP Pads Calibrt*/  argument
89 #define GTPCI_C(p)		(0x0c00 | ((p) << 7))	/* Command */  argument
110 #define GTPCI_M(p)		(0x0d00 | ((p) << 7))	/* Mode */  argument
111 #define GTPCI_R(p)		(0x0c04 | ((p) << 7))	/* Retry */  argument
112 #define GTPCI_DT(p)		(0x0d04 | ((p) << 7))	/* Discard Timer */  argument
113 #define GTPCI_MSITT(p)		(0x0c38 | ((p) << 7))	/* MSI Trigger Timer */  argument
114 #define GTPCI_AC(p)		(0x1d00 | ((p) << 7))	/* Arviter Control */  argument
119 #define GTPCI_P2PC(p)		(0x1d14 | ((p) << 7))	/* P2P Configuration */  argument
123 #define GTPCI_ACBL(p, N)	(0x1e00	| ((p) << 7) | ((N) << 4))  argument
166 #define GTPCI_ACBH(p, N)	(0x1e04	| ((p) << 7) | ((N) << 4))  argument
168 #define GTPCI_ACS(p, N)		(0x1e08	| ((p) << 7) | ((N) << 4))  argument
180 #define GTPCI_CA(p)		(0x0cf8 ^ ((p) << 7))	/* Configuration Addr */  argument
182 #define GTPCI_CD(p)		(0x0cfc ^ ((p) << 7))	/* Configuration Data */  argument
184 #define GTPCI_IA(p)		(0x0c34 | ((p) << 7)	/* Intr Acknowledge */  argument
187 #define GTPCI_SERRM(p)		(0x0c28 | ((p) << 7)	/* SERRn Mask */  argument
188 #define GTPCI_IC(p)		(0x0d58 | ((p) << 7)	/* Interrupt Cause */  argument
189 #define GTPCI_IM(p)		(0x0d5c | ((p) << 7)	/* Interrupt Mask */  argument
190 #define GTPCI_EAL(p)		(0x0d40 | ((p) << 7)	/* Error Addr (Low) */  argument
191 #define GTPCI_EAH(p)		(0x0d44 | ((p) << 7)	/* Error Addr (High) */  argument
192 #define GTPCI_EC(p)		(0x0d50 | ((p) << 7)	/* Error Command */  argument