Lines Matching +full:no +full:- +full:ct
3 /*-
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
38 * Internal registers are read-writable, except where noted.
45 #define MICR_CTVIS 0x04 /* CT vector includes status */
48 #define MICR_NV 0x20 /* No Vector (NV) */
54 #define MCCR_CT1GT2 0x01 /* CT 1 /OUTPUT gates CT 2 */
55 #define MCCR_CT1TR2 0x02 /* CT 1 /OUTPUT triggers CT 2 */
56 #define MCCR_CT1CT2 0x03 /* CT 1 /OUTPUT is CT 2's COUNT */
97 #define Z8536_CTCSR1 0x0A /* CT 1 Command and Status */
98 #define Z8536_CTCSR2 0x0B /* CT 2 Command and Status */
99 #define Z8536_CTCSR3 0x0C /* CT 3 Command and Status */
129 /* Bytewise access to current count registers (read-only) */
130 #define Z8536_CTCCR1_MSB 0x10 /* CT 1 Current Count MSB */
131 #define Z8536_CTCCR1_LSB 0x11 /* CT 1 Current Count LSB */
132 #define Z8536_CTCCR2_MSB 0x12 /* CT 2 Current Count MSB */
133 #define Z8536_CTCCR2_LSB 0x13 /* CT 2 Current Count LSB */
134 #define Z8536_CTCCR3_MSB 0x14 /* CT 3 Current Count MSB */
135 #define Z8536_CTCCR3_LSB 0x15 /* CT 3 Current Count LSB */
138 #define Z8536_CTTCR1_MSB 0x16 /* CT 1 Time Constant MSB */
139 #define Z8536_CTTCR1_LSB 0x17 /* CT 1 Time Constant LSB */
140 #define Z8536_CTTCR2_MSB 0x18 /* CT 2 Time Constant MSB */
141 #define Z8536_CTTCR2_LSB 0x19 /* CT 2 Time Constant LSB */
142 #define Z8536_CTTCR3_MSB 0x1A /* CT 3 Time Constant MSB */
143 #define Z8536_CTTCR3_LSB 0x1B /* CT 3 Time Constant LSB */
146 #define Z8536_CTMSR1 0x1C /* CT 1 Mode Specification */
147 #define Z8536_CTMSR2 0x1D /* CT 2 Mode Specification */
148 #define Z8536_CTMSR3 0x1E /* CT 3 Mode Specification */
150 #define CTMS_DCS_ONESHOT 0x01 /* One-Shot Output */
189 * 0 1 "and" mode, transition-triggered interrupt
190 * 1 0 "or" mode, transition-triggered interrupt
191 * 1 1 "or-priority encoded vector" mode, level-
197 #define PMSR_PMS_AND 0x02 /* "and" mode, transition-triggered */
198 #define PMSR_PMS_OR 0x04 /* "or" mode, transition-triggered */
200 * "or-priority encoded vector" mode, level-triggered interrupt
222 * Bits 0-2 set deskew timer for output ports
225 * 0 0 0 REQUEST/-WAIT disabled
226 * 0 0 1 output -WAIT
227 * 0 1 1 input -WAIT
240 * 1 1 three-wire-handshake