406 		    s->sm_ddr4.ddr4_mod_type <  in spdmem_common_attach()
408 			type = spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type];  in spdmem_common_attach()
419 		if ((s->sm_ddr4.ddr4_hybrid)  in spdmem_common_attach()
420 		    && (s->sm_ddr4.ddr4_hybrid_media == 1))  in spdmem_common_attach()
911 	print_part(s->sm_ddr4.ddr4_part_number,  in decode_ddr4()
912 	    sizeof(s->sm_ddr4.ddr4_part_number));  in decode_ddr4()
914 	if (s->sm_ddr4.ddr4_mod_type < __arraycount(spdmem_ddr4_module_types))  in decode_ddr4()
916 		    spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type]);  in decode_ddr4()
918 		(s->sm_ddr4.ddr4_bus_width_extension) ? "" : "no ",  in decode_ddr4()
919 		(s->sm_ddr4.ddr4_has_therm_sensor) ? "" : "no ");  in decode_ddr4()
934 	dimm_size = (s->sm_ddr4.ddr4_capacity + 28)	/* chip_capacity */  in decode_ddr4()
937 		     + (s->sm_ddr4.ddr4_primary_bus_width + 3); /* bus width */  in decode_ddr4()
938 	switch (s->sm_ddr4.ddr4_device_width) {		/* DRAM width */  in decode_ddr4()
952 		    (s->sm_ddr4.ddr4_package_ranks + 1); /* log.ranks/DIMM */  in decode_ddr4()
953 		if (s->sm_ddr4.ddr4_signal_loading == 2) {  in decode_ddr4()
954 			dimm_size *= (s->sm_ddr4.ddr4_diecount + 1);  in decode_ddr4()
962 #define	__DDR4_VALUE(field) ((s->sm_ddr4.ddr4_##field##_mtb * 125 +	\  in decode_ddr4()
963 			     s->sm_ddr4.ddr4_##field##_ftb) - 		\  in decode_ddr4()
964 			    ((s->sm_ddr4.ddr4_##field##_ftb > 127)?256:0))  in decode_ddr4()
972 			  1 << (s->sm_ddr4.ddr4_primary_bus_width + 3),  in decode_ddr4()
975 	ranks = s->sm_ddr4.ddr4_package_ranks + 1;  in decode_ddr4()
978 	    s->sm_ddr4.ddr4_rows + 12, s->sm_ddr4.ddr4_cols + 9,  in decode_ddr4()
979 	    ranks, (ranks > 1) ? ((s->sm_ddr4.ddr4_rank_mix == 1)  in decode_ddr4()
981 	    1 << (2 + s->sm_ddr4.ddr4_logbanks),  in decode_ddr4()
982 	    1 << s->sm_ddr4.ddr4_bankgroups);  in decode_ddr4()
990 	tRAS_clocks = (s->sm_ddr4.ddr4_tRASmin_msb * 256 +  in decode_ddr4()
991 		       s->sm_ddr4.ddr4_tRASmin_lsb) * 125 * 1000 / cycle_time;  in decode_ddr4()