776 	mtb = (u_int)s->sm_ddr3.ddr3_mtb_dividend * 1000 /  in ddr3_value_pico()
777 	    s->sm_ddr3.ddr3_mtb_divisor;  in ddr3_value_pico()
778 	ftb = (u_int)s->sm_ddr3.ddr3_ftb_dividend * 1000 /  in ddr3_value_pico()
779 	    s->sm_ddr3.ddr3_ftb_divisor;  in ddr3_value_pico()
790 	ddr3_value_pico(s, s->sm_ddr3.ddr3_##field##_mtb,	\
791 	    s->sm_ddr3.ddr3_##field##_ftb)
799 	print_part(s->sm_ddr3.ddr3_part, sizeof(s->sm_ddr3.ddr3_part));  in decode_ddr3()
802 	if (s->sm_ddr3.ddr3_mod_type ==  in decode_ddr3()
804 	    s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM)  in decode_ddr3()
807 		(s->sm_ddr3.ddr3_hasECC)?"":"no ",  in decode_ddr3()
808 		(s->sm_ddr3.ddr3_has_therm_sensor)?"":"no ");  in decode_ddr3()
818 	dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 +  in decode_ddr3()
819 		    (s->sm_ddr3.ddr3_datawidth + 3) -  in decode_ddr3()
820 		    (s->sm_ddr3.ddr3_chipwidth + 2);  in decode_ddr3()
821 	dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1);  in decode_ddr3()
824 	bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3);  in decode_ddr3()
831 	    s->sm_ddr3.ddr3_rows + 12, s->sm_ddr3.ddr3_cols + 9,  in decode_ddr3()
832 	    1 << (s->sm_ddr3.ddr3_logbanks + 3),  in decode_ddr3()
833 	    s->sm_ddr3.ddr3_physbanks + 1,  in decode_ddr3()
843 	    __DDR3_CYCLES((s->sm_ddr3.ddr3_tRAS_msb * 256  in decode_ddr3()
844 		+ s->sm_ddr3.ddr3_tRAS_lsb) * s->sm_ddr3.ddr3_mtb_dividend  in decode_ddr3()
845 		/ s->sm_ddr3.ddr3_mtb_divisor * 1000));  in decode_ddr3()
850 	if (!s->sm_ddr3.ddr3_NOT15V || s->sm_ddr3.ddr3_135V  in decode_ddr3()
851 	    || s->sm_ddr3.ddr3_125V) {  in decode_ddr3()
853 		if (!s->sm_ddr3.ddr3_NOT15V)  in decode_ddr3()
855 		if (s->sm_ddr3.ddr3_135V)  in decode_ddr3()
857 		if (s->sm_ddr3.ddr3_125V)  in decode_ddr3()