Lines Matching defs:nvm_identify_controller

409 struct nvm_identify_controller {  struct
412 	uint16_t	vid;		/* PCI Vendor ID */
413 	uint16_t	ssvid;		/* PCI Subsystem Vendor ID */
415 	uint8_t		sn[20];		/* Serial Number */
416 	uint8_t		mn[40];		/* Model Number */
417 	uint8_t		fr[8];		/* Firmware Revision */
419 	uint8_t		rab;		/* Recommended Arbitration Burst */
420 	uint8_t		ieee[3];	/* IEEE OUI Identifier */
422 	uint8_t		cmic;		/* Controller Multi-Path I/O and
424 	uint8_t		mdts;		/* Maximum Data Transfer Size */
426 	uint16_t	cntlid;		/* Controller ID */
427 	uint32_t	ver;		/* Version */
429 	uint32_t	rtd3r;		/* RTD3 Resume Latency */
430 	uint32_t	rtd3e;		/* RTD3 Enter Latency */
432 	uint32_t	oaes;		/* Optional Asynchronous Events Supported */
433 	uint32_t	ctrattr;	/* Controller Attributes */
435 	uint8_t		_reserved1[12];
437 	uint8_t		fguid[16];	/* FRU Globally Unique Identifier */
439 	uint8_t		_reserved2[128];
443 	uint16_t	oacs;		/* Optional Admin Command Support */
453 	uint8_t		acl;		/* Abort Command Limit */
454 	uint8_t		aerl;		/* Asynchronous Event Request Limit */
456 	uint8_t		frmw;		/* Firmware Updates */
460 	uint8_t		lpa;		/* Log Page Attributes */
463 	uint8_t		elpe;		/* Error Log Page Entries */
464 	uint8_t		npss;		/* Number of Power States Support */
466 	uint8_t		avscc;		/* Admin Vendor Specific Command
468 	uint8_t		apsta;		/* Autonomous Power State Transition
472 	uint16_t	wctemp;		/* Warning Composite Temperature
474 	uint16_t	cctemp;		/* Critical Composite Temperature
477 	uint16_t	mtfa;		/* Maximum Time for Firmware Activation */
479 	uint32_t	hmpre;		/* Host Memory Buffer Preferred Size */
480 	uint32_t	hmmin;		/* Host Memory Buffer Minimum Size */
482 	struct {
485 	} __packed untncap;		/* Name space capabilities:
489 	uint32_t	rpmbs;		/* Replay Protected Memory Block Support */
491 	uint16_t	edstt;		/* Extended Device Self-test Time */
492 	uint8_t		dsto;		/* Device Self-test Options */
494 	uint8_t		fwug;		/* Firmware Update Granularity */
496 	uint16_t	kas;		/* Keep Alive Support */
498 	uint16_t	hctma;		/* Host Controlled Thermal Management
500 	uint16_t	mntmt;		/* Minimum Thermal Management Temperature */
501 	uint16_t	mxtmt;		/* Maximum Thermal Management Temperature */
503 	uint32_t	sanicap;	/* Sanitize Capabilities */
505 	uint8_t		_reserved3[180];
509 	uint8_t		sqes;		/* Submission Queue Entry Size */
512 	uint8_t		cqes;		/* Completion Queue Entry Size */
516 	uint16_t	maxcmd;		/* Maximum Outstanding Commands */
518 	uint32_t	nn;		/* Number of Namespaces */
520 	uint16_t	oncs;		/* Optional NVM Command Support */
528 	uint16_t	fuses;		/* Fused Operation Support */
530 	uint8_t		fna;		/* Format NVM Attributes */
534 	uint8_t		vwc;		/* Volatile Write Cache */
559 NVME_CTASSERT(sizeof(struct nvm_identify_controller) == 4096, "bad size for nvm_identify_controller…  argument