Lines Matching defs:regsp
535 struct com_regs *regsp = &sc->sc_regs;
570 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
572 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
573 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) {
577 memcpy(regsp, &comcons_info.regs, sizeof(*regsp));
635 CSR_WRITE_1(regsp, COM_REG_FIFO,
643 CSR_WRITE_1(regsp, COM_REG_FIFO,
656 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
660 CSR_WRITE_1(regsp, COM_REG_FIFO,
669 CSR_WRITE_1(regsp, COM_REG_FIFO,
673 CSR_WRITE_1(regsp, COM_REG_FIFO,
676 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
678 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
697 lcr = CSR_READ_1(regsp, COM_REG_LCR);
698 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
699 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
700 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
701 CSR_WRITE_1(regsp, COM_REG_LCR,
703 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
713 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
735 lcr = CSR_READ_1(regsp, COM_REG_LCR);
736 CSR_WRITE_1(regsp, COM_REG_LCR,
738 CSR_WRITE_1(regsp, COM_REG_FIFO,
740 iir1 = CSR_READ_1(regsp, COM_REG_IIR);
741 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
742 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
743 CSR_WRITE_1(regsp, COM_REG_FIFO,
745 iir2 = CSR_READ_1(regsp, COM_REG_IIR);
747 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
755 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
766 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
824 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) &&
825 regsp->cr_iobase == comkgdbregs.cr_iobase) {
858 struct com_regs *regsp = &sc->sc_regs;
865 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
866 (void) CSR_READ_1(regsp, COM_REG_IIR);
872 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
874 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
879 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
881 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
883 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
887 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
889 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
891 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
893 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
895 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1755 struct com_regs *regsp = &sc->sc_regs;
1767 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)
1774 CSR_READ_1(regsp, COM_REG_RXDATA);
1788 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
1790 CSR_WRITE_1(regsp, COM_REG_FIFO,
1800 struct com_regs *regsp = &sc->sc_regs;
1806 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1808 CSR_WRITE_1(regsp, COM_REG_IER, 0);
1812 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1819 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1820 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1824 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
1827 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1828 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1829 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1831 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1832 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1833 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1835 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
1837 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1852 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1855 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1856 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1859 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1863 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1865 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1869 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1912 struct com_regs *regsp= &sc->sc_regs;
1924 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
1933 struct com_regs *regsp = &sc->sc_regs;
1965 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1975 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2204 struct com_regs *regsp = &sc->sc_regs;
2213 KASSERT(regsp != NULL);
2216 iir = CSR_READ_1(regsp, COM_REG_IIR);
2222 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--)
2231 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2232 iir = CSR_READ_1(regsp, COM_REG_IIR);
2239 (void)CSR_READ_1(regsp, COM_REG_USR);
2240 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
2241 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
2242 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2243 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2244 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2245 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2246 CSR_WRITE_1(regsp, COM_REG_HALT,
2249 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0;
2255 CSR_READ_1(regsp, COM_REG_HALT),
2256 CSR_READ_1(regsp, COM_REG_USR));
2260 CSR_WRITE_1(regsp, COM_REG_HALT, 0);
2261 (void)CSR_READ_1(regsp, COM_REG_USR);
2263 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2264 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2265 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2266 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2284 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2307 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA);
2318 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2363 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2367 (void) CSR_READ_1(regsp, COM_REG_RXDATA);
2372 msr = CSR_READ_1(regsp, COM_REG_MSR);
2408 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&
2421 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2447 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2454 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2463 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))
2493 com_common_getc(dev_t dev, struct com_regs *regsp)
2512 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2517 c = CSR_READ_1(regsp, COM_REG_RXDATA);
2518 stat = CSR_READ_1(regsp, COM_REG_IIR);
2529 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead)
2535 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2537 cin = CSR_READ_1(regsp, COM_REG_RXDATA);
2538 stat = CSR_READ_1(regsp, COM_REG_IIR);
2545 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)
2548 CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2549 COM_BARRIER(regsp, BR | BW);
2558 cominit(struct com_regs *regsp, int rate, int frequency, int type,
2562 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0,
2563 ®sp->cr_ioh))
2568 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2575 CSR_WRITE_2(regsp, COM_REG_DLBL, rate);
2579 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2580 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2582 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2583 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2584 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2587 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2588 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2591 CSR_WRITE_1(regsp, COM_REG_FIFO,
2595 CSR_WRITE_1(regsp, COM_REG_FIFO,
2612 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2615 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2616 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2619 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2623 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2625 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2630 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2632 CSR_WRITE_1(regsp, COM_REG_IER, 0);
2638 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type,
2643 comcons_info.regs = *regsp;
2714 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type,
2719 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
2720 regsp->cr_iobase == comcons_info.regs.cr_iobase) {
2724 comkgdbregs = *regsp;
2728 comkgdbregs = *regsp;