Lines Matching refs:int64_t

38 int64_t	hv_api_get_version(uint64_t api_group,
41 int64_t	hv_api_set_version(uint64_t api_group,
52 int64_t hv_mach_desc(paddr_t buffer, psize_t *length);
61 int64_t	hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries);
68 int64_t	hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data);
69 int64_t	hv_cpu_myid(uint64_t *cpuid);
77 int64_t	hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags);
78 int64_t	hv_mmu_demap_ctx(uint64_t context, uint64_t flags);
79 int64_t	hv_mmu_demap_all(uint64_t flags);
80 int64_t	hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags);
81 int64_t	hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags);
82 int64_t	hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte,
84 int64_t	hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags);
112 int64_t	hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr);
113 int64_t	hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr);
121 int64_t	hv_mem_scrub(paddr_t raddr, psize_t length);
122 int64_t	hv_mem_sync(paddr_t raddr, psize_t length);
130 int64_t	hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino,
132 int64_t	hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled);
133 int64_t	hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled);
134 int64_t	hv_intr_getstate(uint64_t sysino, uint64_t *intr_state);
135 int64_t	hv_intr_setstate(uint64_t sysino, uint64_t intr_state);
136 int64_t	hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid);
137 int64_t	hv_intr_settarget(uint64_t sysino, uint64_t cpuid);
148 int64_t	hv_vintr_getcookie(uint64_t devhandle, uint64_t devino,
150 int64_t	hv_vintr_setcookie(uint64_t devhandle, uint64_t devino,
152 int64_t	hv_vintr_getenabled(uint64_t devhandle, uint64_t devino,
154 int64_t	hv_vintr_setenabled(uint64_t devhandle, uint64_t devino,
156 int64_t	hv_vintr_getstate(uint64_t devhandle, uint64_t devino,
158 int64_t	hv_vintr_setstate(uint64_t devhandle, uint64_t devino,
160 int64_t	hv_vintr_gettarget(uint64_t devhandle, uint64_t devino,
162 int64_t	hv_vintr_settarget(uint64_t devhandle, uint64_t devino,
171 int64_t	hv_tod_get(uint64_t *tod);
172 int64_t	hv_tod_set(uint64_t tod);
180 int64_t	hv_cons_getchar(int64_t *ch);
181 int64_t	hv_cons_putchar(int64_t ch);
182 int64_t	hv_api_putchar(int64_t ch);
193 int64_t	hv_soft_state_set(uint64_t software_state,
205 int64_t	hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid,
208 int64_t	hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid,
210 int64_t	hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid,
212 int64_t	hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr,
215 int64_t	hv_pci_config_get(uint64_t devhandle, uint64_t pci_device,
218 int64_t	hv_pci_config_put(uint64_t devhandle, uint64_t pci_device,
231 int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid,
233 int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid,
236 int64_t hv_pci_msiq_getvalid(uint64_t devhandle, uint64_t msiqid,
238 int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid,
246 int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid,
248 int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid,
256 int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid,
258 int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid,
260 int64_t hv_pci_msiq_gettail(uint64_t devhandle, uint64_t msiqid,
263 int64_t hv_pci_msi_getvalid(uint64_t devhandle, uint64_t msinum,
265 int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum,
273 int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum,
275 int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum,
278 int64_t hv_pci_msi_getstate(uint64_t devhandle, uint64_t msinum,
280 int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum,
288 int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg,
290 int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg,
293 int64_t hv_pci_msg_getvalid(uint64_t devhandle, uint64_t msg,
295 int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg,
313 int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr,
315 int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr,
317 int64_t hv_ldc_tx_get_state(uint64_t ldc_id, uint64_t *head_offset,
319 int64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
320 int64_t hv_ldc_rx_qconf(uint64_t ldc_id, paddr_t base_raddr,
322 int64_t hv_ldc_rx_qinfo(uint64_t ldc_id, paddr_t *base_raddr,
324 int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset,
326 int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
334 int64_t	hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr,
336 int64_t	hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr,
338 int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie,
346 int64_t hv_ldc_mapin(uint64_t ldc_id, uint64_t cookie, paddr_t *raddr,
348 int64_t hv_ldc_unmap(paddr_t raddr, uint64_t *perms);
356 int64_t	hv_rng_get_diag_control(void);
357 int64_t	hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta);
358 int64_t	hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout,
368 int64_t	hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta);
369 int64_t	hv_rng_data_read(paddr_t raddr, uint64_t *delta);
398 int64_t sun4v_intr_devino_to_sysino(uint64_t, uint64_t, uint64_t *);
399 int64_t sun4v_intr_setcookie(uint64_t, uint64_t, uint64_t);
400 int64_t sun4v_intr_setenabled(uint64_t, uint64_t, uint64_t);
401 int64_t	sun4v_intr_setstate(uint64_t, uint64_t, uint64_t);
402 int64_t	sun4v_intr_settarget(uint64_t, uint64_t, uint64_t);