178 struct cpu_info {  struct
191 	 * SPARC cpu_info structures live at two VAs: one global  argument
199 	struct cpu_info * volatile ci_self;  argument
201 	int		ci_cpuid;	/* CPU index (see cpus[] array) */
204 	int		*ctx_tbl;	/* [4m] SRMMU-edible context table */
205 	paddr_t		ctx_tbl_pa;	/* [4m] ctx table physical address */
208 	struct cacheinfo	cacheinfo;	/* see above */
211 	volatile int	flags;		/* see CPUFLG_xxx, below */
214 	volatile struct counter_4m	*counterreg_4m;
217 	volatile struct icr_pi	*intreg_4m;
228 	int		sun4_mmu3l;	/* [4]: 3-level MMU present */
234 	int		ci_idepth;		/* Interrupt depth */
241 	struct	lwp	*ci_curlwp;		/* CPU owner */
242 	struct	lwp	*ci_onproc;		/* current user LWP / kthread */
243 	struct	lwp 	*fplwp;			/* FPU owner */
245 	int		ci_mtx_count;
246 	int		ci_mtx_oldspl;
251 	void		*eintstack;		/* End of interrupt stack */
253 	void		*redzone;		/* DEBUG: stack red zone */
256 	struct	pcb	*curpcb;		/* CPU's PCB & kernel stack */
259 	void	(*get_syncflt)(void);		/* Not C-callable */
260 	int	(*get_asyncflt)(u_int *, u_int *);
263 	struct {
266 	} syncfltdump;
276 	void	(*cache_flush)(void *, u_int);
277 	void	(*vcache_flush_page)(int, int);
278 	void	(*sp_vcache_flush_page)(int, int);
279 	void	(*ft_vcache_flush_page)(int, int);
280 	void	(*vcache_flush_segment)(int, int, int);
281 	void	(*sp_vcache_flush_segment)(int, int, int);
282 	void	(*ft_vcache_flush_segment)(int, int, int);
283 	void	(*vcache_flush_region)(int, int);
284 	void	(*sp_vcache_flush_region)(int, int);
285 	void	(*ft_vcache_flush_region)(int, int);
286 	void	(*vcache_flush_context)(int);
287 	void	(*sp_vcache_flush_context)(int);
288 	void	(*ft_vcache_flush_context)(int);
291 	void	(*sp_vcache_flush_range)(int, int, int);
292 	void	(*ft_vcache_flush_range)(int, int, int);
294 	void	(*pcache_flush_page)(paddr_t, int);
295 	void	(*pure_vcache_flush)(void);
296 	void	(*cache_flush_all)(void);
299 	void	(*zero_page)(paddr_t);
300 	void	(*copy_page)(paddr_t, paddr_t);
303 	void *	vpage[2];
304 	int	*vpage_pte[2];		/* pte location of vpage[] */
306 	void	(*cache_enable)(void);
308 	int	cpu_type;	/* Type: see CPUTYP_xxx below */
311 	struct xpmsg	msg_lev15;
314 	int		node;		/* PROM node for this CPU */
315 	int		mid;		/* Module ID for MP systems */
316 	int		mbus;		/* 1 if CPU is on MBus */
317 	int		mxcc;		/* 1 if a MBus-level MXCC is present */
318 	const char	*cpu_longname;	/* CPU model */
319 	int		cpu_impl;	/* CPU implementation code */
320 	int		cpu_vers;	/* CPU version code */
321 	int		mmu_impl;	/* MMU implementation code */
322 	int		mmu_vers;	/* MMU version code */
323 	int		master;		/* 1 if this is bootup CPU */
325 	vaddr_t		mailbox;	/* VA of CPU's mailbox */
327 	int		mmu_ncontext;	/* Number of contexts supported */
328 	int		mmu_nregion; 	/* Number of regions supported */
329 	int		mmu_nsegment;	/* [4/4c] Segments */
330 	int		mmu_npmeg;	/* [4/4c] Pmegs */
333 	int		arch;		/* Architecture: CPU_SUN4x */
334 	int		class;		/* Class: SuperSPARC, microSPARC... */
335 	int		classlvl;	/* Iteration in class: 1, 2, etc. */
359 	void	(*hotfix)(struct cpu_info *);  argument
384 	 * Start/End VA's of this cpu_info region; we upload the other pages  argument
387 	vaddr_t	ci_free_sva1, ci_free_eva1, ci_free_sva2, ci_free_eva2;
389 	struct evcnt ci_savefpstate;
390 	struct evcnt ci_savefpstate_null;
391 	struct evcnt ci_xpmsg_mutex_fail;
392 	struct evcnt ci_xpmsg_mutex_fail_call;
416 #define	cpuinfo			(*(struct cpu_info *)CPUINFO_VA)  argument