Lines Matching defs:cg14ctl
70 struct cg14ctl { struct
71 volatile uint8_t ctl_mctl; /* main control register */
85 volatile uint8_t ctl_ppr; /* packed pixel register */
86 volatile uint8_t ctl_tmsr0; /* test status reg. 0 */
87 volatile uint8_t ctl_tmsr1; /* test status reg. 1 */
88 volatile uint8_t ctl_msr; /* master status register */
89 volatile uint8_t ctl_fsr; /* fault status register */
90 volatile uint8_t ctl_rsr; /* revision status register */
93 volatile uint8_t ctl_ccr; /* clock control register */
99 volatile uint32_t ctl_tmr; /* test mode readback */
100 volatile uint8_t ctl_mod; /* monitor data register */
104 volatile uint8_t ctl_acr; /* aux control register */
107 uint8_t m_pad0[6]; /* Reserved */
108 uint16_t m_hct; /* Horizontal Counter */
109 uint16_t m_vct; /* Vertical Counter */
110 uint16_t m_hbs; /* Horizontal Blank Start */
111 uint16_t m_hbc; /* Horizontal Blank Clear */
112 uint16_t m_hss; /* Horizontal Sync Set */
113 uint16_t m_hsc; /* Horizontal Sync Set */
114 uint16_t m_csc; /* Composite sync clear */
115 uint16_t m_vbs; /* Vertical blank start */
116 uint16_t m_vbc; /* Vertical Blank Clear */
117 uint16_t m_vss; /* Verical Sync Set */
118 uint16_t m_vsc; /* Verical Sync Clear */
119 uint16_t m_xcs; /* XXX Gone in VSIMM 2 */
120 uint16_t m_xcc; /* XXX Gone in VSIMM 2 */
121 uint16_t m_fsa; /* Fault status address */
122 uint16_t m_adr; /* Address register (autoincrements) */
123 uint8_t m_pad2[0xce]; /* Reserved */
126 uint8_t m_pcg[0x100]; /* Pixel Clock generator regs */