Lines Matching refs:__PPCBITS
41 #define __PPCBITS(m, n) (((1 << ((n) - (m) + 1)) - 1) << (31 - (m))) macro
44 #define __PPCBITS(m,n) __BITS(31-(n),31-(m)) macro
50 #define BPTR_BOOT_PAGE __PPCBITS(8,31) /* high 24 bits of phys addr */
58 #define BNDS_SA __PPCBITS(4,15)
60 #define BNDS_EA __PPCBITS(20,31)
72 #define SDRAM_CFG_TYPE __PPCBITS(5,7)
76 #define SDRAM_CFG_DBW __PPCBITS(11,12)
96 #define CATTR_BNUM __PPCBITS(1,3)
97 #define CATTR_TSIZ __PPCBITS(5,7)
98 #define CATTR_TSRC __PPCBITS(11,15)
99 #define CATTR_TTYP __PPCBITS(18,19)
106 #define ERR_SBE_SBET __PPCBITS(8,15)
107 #define ERR_SBE_SBEC __PPCBITS(24,31)
163 #define PEXOWAR_TC __PPCBITS(8,10) /* traffic class PCIEX only */
172 #define PEXOWAR_RTT __PPCBITS(12,15) /* read transaction type */
176 #define PEXOWAR_WTT __PPCBITS(16,19) /* write transaction type */
180 #define PEXOWAR_OWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */
185 #define PEXIWAR_TRGT __PPCBITS(8,11) /* traffic class PCIEX only */
191 #define PEXIWAR_RTT __PPCBITS(12,15) /* read transaction type */
196 #define PEXIWAR_WTT __PPCBITS(16,19) /* write transaction type */
201 #define PEXIWAR_IWS __PPCBITS(26,31) /* encoded as 2^(N+1) bytes */
281 #define L2CTL_L2SIZ __PPCBITS(2,3)
286 #define L2CTL_L2SRAM __PPCBITS(13,15)
290 #define L2CTL_L2LFRID __PPCBITS(22,23)
292 #define L2CTL_L2STASH __PPCBITS(30,31)
321 #define SPMODE_HO_ADJ __PPCBITS(13,15) /* Data output hold adjustment */
322 #define SPMODE_TXTHR __PPCBITS(18,23) /* Tx FIFO Threshold: 1-32 */
323 #define SPMODE_RXTHR __PPCBITS(27,31) /* Rx FIFO threshold: 0-31 */
325 #define SPIE_RXCNT __PPCBITS(2,7) /* current number of full Rx FIFO bytes */
326 #define SPIE_TXCNT __PPCBITS(10,15) /* current number of full Tx FIFO bytes */
343 #define SPCOM_CS __PPCBITS(0,1) /* Chip select: 0=CS0, 1=CS1, 2=CS2(P1025), 3=CS3(P1025) */
349 #define SPCOM_RXSKIP __PPCBITS(8,15) /* if RxSKIP != 0: Number of characters skipped for reception …
350 #define SPCOM_TRANLEN __PPCBITS(16,31) /* Transaction length */
362 #define SPMODEn_PM __PPCBITS(4,7) /* Prescale modulus select */
365 #define SPMODEn_LEN __PPCBITS(12,15) /* Character length in bits per character */
366 #define SPMODEn_CSBEF __PPCBITS(16,19) /* CS assertion time in bits before frame start */
367 #define SPMODEn_CSAFT __PPCBITS(20,23) /* CS assertion time in bits after frame end */
368 #define SPMODEn_CSCG __PPCBITS(24,28) /* Clock gap */
420 #define E500_RATIO2 __PPCBITS(2,7)
422 #define E500_RATIO __PPCBITS(10,15)
426 #define PLAT_RATIO __PPCBITS(26,30)
429 #define PORBMSR_BCFG __PPCBITS(0,1)
430 #define PORBMSR_HA __PPCBITS(13,15)
448 #define PORDEVSR_ECP1 __PPCBITS(6,7)
452 #define PORDEVSR_IOSEL_P1023 __PPCBITS(9,10)
457 #define PORDEVSR_IOSEL __PPCBITS(9,12)
505 #define PORDEVSR_ECP2 __PPCBITS(18,19)
506 #define PORDEVSR_ECP3 __PPCBITS(20,21)
507 #define PORDEVSR_ECP4 __PPCBITS(22,23)
542 #define PMUXCR_USB_PCTL __PPCBITS(6,5)
658 #define BR_BA __PPCBITS(0,16)
659 #define BR_XBA __PPCBITS(17,18)
660 #define BR_PS __PPCBITS(19,20)
664 #define BR_DECC __PPCBITS(21,22)
669 #define BR_MSEL __PPCBITS(24,26)
676 #define BR_ATOM __PPCBITS(28,29)
682 #define OR_AM __PPCBITS(0,16)
683 #define OR_XAM __PPCBITS(17,18)
686 #define OR_ACS __PPCBITS(21,22)
688 #define OR_SCY __PPCBITS(24,27)
718 #define MDR_AS3 __PPCBITS(0,7)
719 #define MDR_AS2 __PPCBITS(8,15)
720 #define MDR_AS1 __PPCBITS(16,23)
721 #define MDR_AS0 __PPCBITS(24,31)
758 #define LTEATR_SRCID __PPCBITS(11,15)
759 #define LTEATR_PB __PPCBITS(16,19)
760 #define LTEATR_BNK __PPCBITS(20,27)
764 #define LTECCR_SBCE __PPCBITS(12,15)
765 #define LTECCR_MBUE __PPCBITS(28,31)
770 #define FMR_CWTO __PPCBITS(16,19)
773 #define FMR_AL __PPCBITS(26,27)
774 #define FMR_OP __PPCBITS(30,31)
776 #define FIR_OP0 __PPCBITS(0,3)
777 #define FIR_OP1 __PPCBITS(4,7)
778 #define FIR_OP2 __PPCBITS(8,11)
779 #define FIR_OP3 __PPCBITS(12,15)
780 #define FIR_OP4 __PPCBITS(16,19)
781 #define FIR_OP5 __PPCBITS(20,23)
782 #define FIR_OP6 __PPCBITS(24,27)
783 #define FIR_OP7 __PPCBITS(28,31)
801 #define FCR_CMD0 __PPCBITS(0,7)
802 #define FCR_CMD1 __PPCBITS(8,15)
803 #define FCR_CMD2 __PPCBITS(16,23)
804 #define FCR_CMD3 __PPCBITS(24,31)
806 #define FBAR_BLK __PPCBITS(8,31)
808 #define FPAR_S_PI __PPCBITS(17,21) /* Page Index */
810 #define FPAR_S_CI __PPCBITS(23,31) /* Column Index */
811 #define FPAR_L_PI __PPCBITS(14,19) /* Page Index */
813 #define FPAR_L_CI __PPCBITS(21,31) /* Column Index */
815 #define FBCR_BC __PPCBITS(20,31)
824 #define MXMR_OP __PPCBITS(2,3) /* Command opcode */
830 #define MXMR_AM __PPCBITS(5,7) /* Address multiplex size */
831 #define MXMR_DS __PPCBITS(8,9) /* Disable timer period */
836 #define MXMR_G0CL __PPCBITS(10,12) /* General line 0 control */
846 #define MXMR_RLF __PPCBITS(14,17) /* Read loop field */
847 #define MXMR_WLF __PPCBITS(18,21) /* Write loop field */
848 #define MXMR_TLF __PPCBITS(22,25) /* Refresh loop field */
849 #define MXMR_MAS __PPCBITS(26,31) /* Machine Address */
851 #define MRTPR_PTP __PPCBITS(0,7) /* Refresh timers prescaler */