Lines Matching defs:csr
729 int csr;
730 GET_SBIC_csr(regs, csr);
731 printf("sbicwait TIMEO @%d with asr=x%x csr=x%x\n",
732 line, val, csr);
751 u_char csr, asr;
754 GET_SBIC_csr(regs, csr);
756 printf ("%s: abort %s: csr = 0x%02x, asr = 0x%02x\n",
757 device_xname(dev->sc_dev), where, csr, asr);
806 GET_SBIC_csr (regs, csr);
807 QPRINTF(("csr: 0x%02x, asr: 0x%02x\n", csr, asr));
808 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) &&
809 (csr != SBIC_CSR_CMD_INVALID));
880 u_char csr;
902 GET_SBIC_csr(regs, csr); /* clears interrupt also */
903 __USE(csr);
930 sbicerror(struct sbic_softc *dev, u_char csr)
942 printf("%s: csr == 0x%02x\n", device_xname(dev->sc_dev), csr);
956 u_char target = dev->target, lun = dev->lun, asr, csr, id;
1002 GET_SBIC_csr (regs, csr);
1004 QPRINTF(("%02x ", csr));
1009 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) {
1014 sbicnextstate(dev, csr, asr);
1022 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) {
1027 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
1028 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
1029 csr != SBIC_CSR_SEL_TIMEO);
1034 if (csr == SBIC_CSR_SEL_TIMEO) {
1067 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1133 GET_SBIC_csr(regs, csr);
1157 return csr;
1276 * this leaves with one csr to be read
1299 u_char csr, asr;
1340 if ((csr = sbicselectbus(dev)) == 0) {
1346 GET_SBIC_csr(regs, csr);
1348 csr = 0;
1350 if (csr) {
1352 QPRINTF((">ASR:0x%02x CSR:0x%02x< ", asr, csr));
1354 switch (csr) {
1409 still_busy = sbicnextstate(dev, csr, asr);
1429 "CSR:%02x,ASR:%02x\n", csr, asr);
1466 GET_SBIC_csr(regs, csr);
1489 u_char phase, csr;
1505 GET_SBIC_csr(regs, csr);
1506 QPRINTF(("%02x:", csr));
1508 } while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) &&
1509 (csr != SBIC_CSR_S_XFERRED));
1519 sbicerror(dev, csr);
1535 u_char csr, asr, *addr;
1551 if ((csr = sbicselectbus(dev)) == 0)
1626 i = sbicnextstate(dev, csr, asr);
1634 printf("sbicgo: LCI asr:%02x csr:%02x\n",
1635 asr, csr);
1638 GET_SBIC_csr(regs, csr);
1662 u_char asr, csr;
1672 GET_SBIC_csr(regs, csr);
1676 QPRINTF(("intr[0x%x]", csr));
1678 i = sbicnextstate(dev, csr, asr);
1686 printf("sbicgo: LCI asr:%02x csr:%02x\n", asr, csr);
1689 GET_SBIC_csr(regs, csr);
1708 u_char asr, csr = SBIC_CSR_RESET; /* XXX: Quell un-init warning */
1720 GET_SBIC_csr(regs, csr);
1722 QPRINTF(("poll[0x%x]", csr));
1727 i = sbicnextstate(dev, csr, asr);
1740 " CSR:%02x,ASR:%02x\n", csr, asr);
1760 printf("sbicpoll: LCI asr:%02x csr:%02x\n", asr,csr);
1777 u_char asr, csr, *tmpaddr, *msgaddr;
1791 GET_SBIC_selid (regs, csr);
1792 SET_SBIC_selid (regs, csr | SBIC_SID_FROM_SCSI);
1810 GET_SBIC_csr(regs, csr);
1814 printf("sbicmsgin: got %02x csr %02x\n",
1815 *tmpaddr, csr);
1827 GET_SBIC_csr(regs, csr);
1839 printf("msgin done csr 0x%x asr 0x%x msg 0x%x\n",
1840 csr, asr, msgaddr[0]);
1984 GET_SBIC_csr(regs, csr);
1987 QPRINTF(("CLR ACK csr %02x\n", csr));
1999 GET_SBIC_csr(regs, csr);
2006 QPRINTF(("Recving ext msg, csr %02x len %02x\n",
2007 csr, recvlen));
2079 GET_SBIC_csr(regs, csr);
2099 sbicnextstate(struct sbic_softc *dev, u_char csr, u_char asr)
2104 QPRINTF(("next[%02x,%02x]: ",asr,csr));
2106 switch (csr) {
2164 "asr:0x%02x csr:0x%02x\n",
2165 acb->sc_kv.dc_count, asr, csr);
2188 if (SBIC_PHASE(csr) == DATA_IN_PHASE)
2271 printf("Acking unknown msgin CSR:%02x",csr);
2348 if (csr == SBIC_CSR_RSLT_IFY) {
2383 GET_SBIC_csr(regs,csr);
2385 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) ||
2386 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) ||
2387 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {
2401 "not MESG_IN_PHASE %x\n", csr);
2412 (reselect_debug && csr == SBIC_CSR_RSLT_NI)) {
2414 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY",
2430 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY");
2480 csr == SBIC_CSR_RSLT_NI ? "NI" : "IFY", newtarget,
2485 if (csr == SBIC_CSR_RSLT_IFY)
2494 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr);
2511 sbicerror(dev, csr);