Lines Matching refs:VIA1
76 #define PM_SR() via_reg(VIA1, vSR)
77 #define PM_VIA_INTR_ENABLE() via_reg(VIA1, vIER) = 0x90
78 #define PM_VIA_INTR_DISABLE() via_reg(VIA1, vIER) = 0x10
79 #define PM_VIA_CLR_INTR() via_reg(VIA1, vIFR) = 0x90
433 via1_vIER = via_reg(VIA1, vIER);
436 via1_vDirA = via_reg(VIA1, vDirA);
447 via_reg(VIA1, vDirA) = via1_vDirA;
448 via_reg(VIA1, vIER) = via1_vIER;
469 via_reg(VIA1, vIER) = via1_vIER;
477 via1_vDirA = via_reg(VIA1, vDirA);
478 via_reg(VIA1, vDirA) &= 0x7f;
484 via_reg(VIA1, vDirA) = via1_vDirA;
492 via_reg(VIA1, vDirA) = via1_vDirA;
493 via_reg(VIA1, vIER) = via1_vIER;
548 via_reg(VIA1, vDirA) = via1_vDirA;
549 via_reg(VIA1, vIER) = via1_vIER;
569 PM_VIA_CLR_INTR(); /* clear VIA1 interrupt */
631 via_reg(VIA1, vACR) |= 0x0c;
632 via_reg(VIA1, vACR) &= ~0x10;
651 via_reg(VIA1, vACR) |= 0x1c;
666 via_reg(VIA1, vACR) |= 0x1c;
681 via_reg(VIA1, vACR) |= 0x1c;
708 via1_vIER &= via_reg(VIA1, vIER);
709 via_reg(VIA1, vIER) = via1_vIER;
815 via_reg(VIA1, vIER) = via1_vIER;
834 PM_VIA_CLR_INTR(); /* clear VIA1 interrupt */
990 via_reg(VIA1, vIER) = 0x10;
1063 if ((via_reg(VIA1, vIFR) & 0x10) == 0x10)