Lines Matching defs:dvboxfb
60 struct dvboxfb { struct
62 vu_char reset; /* reset register 0x01 */
63 u_char fb_address; /* frame buffer address 0x02 */
64 vu_char interrupt; /* interrupt register 0x03 */
66 vu_char fbwmsb; /* frame buffer width MSB 0x05 */
68 vu_char fbwlsb; /* frame buffer width MSB 0x07 */
70 vu_char fbhmsb; /* frame buffer height MSB 0x09 */
72 vu_char fbhlsb; /* frame buffer height MSB 0x0b */
74 vu_char dwmsb; /* display width MSB 0x0d */
76 vu_char dwlsb; /* display width MSB 0x0f */
78 vu_char dhmsb; /* display height MSB 0x11 */
80 vu_char dhlsb; /* display height MSB 0x13 */
82 vu_char fbid; /* frame buffer id 0x15 */
83 u_char f1[0x47];
84 vu_char fbomsb; /* frame buffer offset MSB 0x5d */
86 vu_char fbolsb; /* frame buffer offset LSB 0x5f */
87 u_char f2[16359];
88 vu_char wbusy; /* Window move in progress 0x4047 */
89 u_char f3[0x405b-0x4047-1];
90 vu_char as_busy; /* Scan accessing frame buf. 0x405B */
91 u_char f4[0x4090-0x405b-1];
92 vu_int fbwen; /* Frame buffer write enable 0x4090 */
93 u_char f5[0x409f-0x4090-4];
94 vu_char wmove; /* Initiate window move. 0x409F */
95 u_char f6[0x40b3-0x409f-1];
96 vu_char fold; /* Byte/longword per pixel 0x40B3 */
97 u_char f7[0x40b7-0x40b3-1];
98 vu_char opwen; /* Overlay plane write enable 0x40B7 */
99 u_char f8[0x40bf-0x40b7-1];
100 vu_char drive; /* Select FB vs. Overlay. 0x40BF */
102 u_char f8a[0x40cb-0x40bf-1];
103 vu_char zconfig; /* Z buffer configuration 0x40CB */
104 u_char f8b[0x40cf-0x40cb-1];
105 vu_char alt_rr; /* Alternate replacement rule 0x40CF */
106 u_char f8c[0x40d3-0x40cf-1];
107 vu_char zrr; /* Z replacement rule 0x40D3 */
109 u_char f9[0x40d7-0x40d3-1];
110 vu_char en_scan; /* Enable scan DTACK. 0x40D7 */
111 u_char f10[0x40ef-0x40d7-1];
112 vu_char rep_rule; /* Replacement rule 0x40EF */
113 u_char f11[0x40f2-0x40ef-1];
114 vu_short source_x; /* Window source X origin 0x40F2 */
115 u_char f12[0x40f6-0x40f2-2];
116 vu_short source_y; /* Window source Y origin 0x40F6 */
117 u_char f13[0x40fa-0x40f6-2];
118 vu_short dest_x; /* Window dest X origin 0x40FA */
119 u_char f14[0x40fe -0x40fa-2];
120 vu_short dest_y; /* Window dest Y origin 0x40FE */
121 u_char f15[0x4102-0x40fe -2];
122 vu_short wwidth; /* Window width 0x4102 */
123 u_char f16[0x4106-0x4102-2];
124 vu_short wheight; /* Window height 0x4106 */
125 u_char f17[0x6003-0x4106-2];
126 vu_char cmapbank; /* Bank select (0 or 1) 0x6003 */
127 u_char f18[0x6007-0x6003-1];
128 vu_char dispen; /* Display enable 0x6007 */
130 u_char f18a[0x600B-0x6007-1];
131 vu_char fbvenp; /* Frame buffer video enable 0x600B */
132 u_char f18b[0x6017-0x600B-1];
133 vu_char fbvens; /* fbvenp blink counterpart 0x6017 */
135 u_char f19[0x6023-0x6017-1];
136 vu_char vdrive; /* Video display mode 0x6023 */
137 u_char f20[0x6083-0x6023-1];
138 vu_char panxh; /* Pan display in X (high) 0x6083 */
139 u_char f21[0x6087-0x6083-1];
140 vu_char panxl; /* Pan display in X (low) 0x6087 */
141 u_char f22[0x608b-0x6087-1];
142 vu_char panyh; /* Pan display in Y (high) 0x608B */
143 u_char f23[0x608f-0x608b-1];
144 vu_char panyl; /* Pan display in Y (low) 0x608F */
145 u_char f24[0x6093-0x608f-1];
146 vu_char zoom; /* Zoom factor 0x6093 */
147 u_char f25[0x6097-0x6093-1];
148 vu_char pz_trig; /* Pan & zoom trigger 0x6097 */
149 u_char f26[0x609b-0x6097-1];
150 vu_char ovly0p; /* Overlay 0 primary map 0x609B */
151 u_char f27[0x609f-0x609b-1];
152 vu_char ovly1p; /* Overlay 1 primary map 0x609F */
153 u_char f28[0x60a3-0x609f-1];
154 vu_char ovly0s; /* Overlay 0 secondary map 0x60A3 */
155 u_char f29[0x60a7-0x60a3-1];
156 vu_char ovly1s; /* Overlay 1 secondary map 0x60A7 */
157 u_char f30[0x60ab-0x60a7-1];
158 vu_char opvenp; /* Overlay video enable 0x60AB */
159 u_char f31[0x60af-0x60ab-1];
160 vu_char opvens; /* Overlay blink enable 0x60AF */
161 u_char f32[0x60b3-0x60af-1];
162 vu_char fv_trig; /* Trigger control registers 0x60B3 */
163 u_char f33[0x60b7-0x60b3-1];
164 vu_char cdwidth; /* Iris cdwidth timing reg. 0x60B7 */
165 u_char f34[0x60bb-0x60b7-1];
166 vu_char chstart; /* Iris chstart timing reg. 0x60BB */
167 u_char f35[0x60bf-0x60bb-1];
168 vu_char cvwidth; /* Iris cvwidth timing reg. 0x60BF */
169 u_char f36[0x6100-0x60bf-1];
170 struct rgb rgb[8]; /* overlay color map */
171 u_char f37[0x6403-0x6100-sizeof(struct rgb)*8];
172 vu_char red0;
173 u_char f38[0x6803-0x6403-1];
174 vu_char green0;
175 u_char f39[0x6c03-0x6803-1];
176 vu_char blue0;
177 u_char f40[0x7403-0x6c03-1];
178 vu_char red1;
179 u_char f41[0x7803-0x7403-1];
180 vu_char green1;
181 u_char f42[0x7c03-0x7803-1];
182 vu_char blue1;
183 u_char f43[0x8012-0x7c03-1];
184 vu_short status1; /* Master Status register 0x8012 */
185 u_char f44[0xC226-0x8012-2];
186 vu_short trans; /* Transparency 0xC226 */
187 u_char f45[0xC23E -0xC226-2];
188 vu_short pstop; /* Pace value control 0xc23e */