Lines Matching defs:dvboxfb
61 struct dvboxfb { struct
62 struct diofbreg regs;
63 uint8_t f2[16359];
64 uint8_t wbusy; /* Window move in progress 0x4047 */
65 uint8_t f3[0x405b-0x4047-1];
66 uint8_t as_busy; /* Scan accessing frame buf. 0x405B */
67 uint8_t f4[0x4090-0x405b-1];
68 uint32_t fbwen; /* Frame buffer write enable 0x4090 */
69 uint8_t f5[0x409f-0x4090-4];
70 uint8_t wmove; /* Initiate window move. 0x409F */
71 uint8_t f6[0x40b3-0x409f-1];
72 uint8_t fold; /* Byte/longword per pixel 0x40B3 */
73 uint8_t f7[0x40b7-0x40b3-1];
74 uint8_t opwen; /* Overlay plane write enable 0x40B7 */
75 uint8_t f8[0x40bf-0x40b7-1];
76 uint8_t drive; /* Select FB vs. Overlay. 0x40BF */
78 uint8_t f8a[0x40cb-0x40bf-1];
79 uint8_t zconfig; /* Z buffer configuration 0x40CB */
80 uint8_t f8b[0x40cf-0x40cb-1];
81 uint8_t alt_rr; /* Alternate replacement rule 0x40CF */
82 uint8_t f8c[0x40d3-0x40cf-1];
83 uint8_t zrr; /* Z replacement rule 0x40D3 */
85 uint8_t f9[0x40d7-0x40d3-1];
86 uint8_t en_scan; /* Enable scan DTACK. 0x40D7 */
87 uint8_t f10[0x40ef-0x40d7-1];
88 uint8_t rep_rule; /* Replacement rule 0x40EF */
89 uint8_t f11[0x40f2-0x40ef-1];
90 uint16_t source_x; /* Window source X origin 0x40F2 */
91 uint8_t f12[0x40f6-0x40f2-2];
92 uint16_t source_y; /* Window source Y origin 0x40F6 */
93 uint8_t f13[0x40fa-0x40f6-2];
94 uint16_t dest_x; /* Window dest X origin 0x40FA */
95 uint8_t f14[0x40fe -0x40fa-2];
96 uint16_t dest_y; /* Window dest Y origin 0x40FE */
97 uint8_t f15[0x4102-0x40fe -2];
98 uint16_t wwidth; /* Window width 0x4102 */
99 uint8_t f16[0x4106-0x4102-2];
100 uint16_t wheight; /* Window height 0x4106 */
101 uint8_t f17[0x6003-0x4106-2];
102 uint8_t cmapbank; /* Bank select (0 or 1) 0x6003 */
103 uint8_t f18[0x6007-0x6003-1];
104 uint8_t dispen; /* Display enable 0x6007 */
106 uint8_t f18a[0x600B-0x6007-1];
107 uint8_t fbvenp; /* Frame buffer video enable 0x600B */
108 uint8_t f18b[0x6017-0x600B-1];
109 uint8_t fbvens; /* fbvenp blink counterpart 0x6017 */
111 uint8_t f19[0x6023-0x6017-1];
112 uint8_t vdrive; /* Video display mode 0x6023 */
113 uint8_t f20[0x6083-0x6023-1];
114 uint8_t panxh; /* Pan display in X (high) 0x6083 */
115 uint8_t f21[0x6087-0x6083-1];
116 uint8_t panxl; /* Pan display in X (low) 0x6087 */
117 uint8_t f22[0x608b-0x6087-1];
118 uint8_t panyh; /* Pan display in Y (high) 0x608B */
119 uint8_t f23[0x608f-0x608b-1];
120 uint8_t panyl; /* Pan display in Y (low) 0x608F */
121 uint8_t f24[0x6093-0x608f-1];
122 uint8_t zoom; /* Zoom factor 0x6093 */
123 uint8_t f25[0x6097-0x6093-1];
124 uint8_t pz_trig; /* Pan & zoom trigger 0x6097 */
125 uint8_t f26[0x609b-0x6097-1];
126 uint8_t ovly0p; /* Overlay 0 primary map 0x609B */
127 uint8_t f27[0x609f-0x609b-1];
128 uint8_t ovly1p; /* Overlay 1 primary map 0x609F */
129 uint8_t f28[0x60a3-0x609f-1];
130 uint8_t ovly0s; /* Overlay 0 secondary map 0x60A3 */
131 uint8_t f29[0x60a7-0x60a3-1];
132 uint8_t ovly1s; /* Overlay 1 secondary map 0x60A7 */
133 uint8_t f30[0x60ab-0x60a7-1];
134 uint8_t opvenp; /* Overlay video enable 0x60AB */
135 uint8_t f31[0x60af-0x60ab-1];
136 uint8_t opvens; /* Overlay blink enable 0x60AF */
137 uint8_t f32[0x60b3-0x60af-1];
138 uint8_t fv_trig; /* Trigger control registers 0x60B3 */
139 uint8_t f33[0x60b7-0x60b3-1];
140 uint8_t cdwidth; /* Iris cdwidth timing reg. 0x60B7 */
141 uint8_t f34[0x60bb-0x60b7-1];
142 uint8_t chstart; /* Iris chstart timing reg. 0x60BB */
143 uint8_t f35[0x60bf-0x60bb-1];
144 uint8_t cvwidth; /* Iris cvwidth timing reg. 0x60BF */
145 uint8_t f36[0x6100-0x60bf-1];
146 struct rgb rgb[8]; /* overlay color map */
147 uint8_t f37[0x6403-0x6100-sizeof(struct rgb)*8];
148 uint8_t red0;
149 uint8_t f38[0x6803-0x6403-1];
150 uint8_t green0;
151 uint8_t f39[0x6c03-0x6803-1];
152 uint8_t blue0;
153 uint8_t f40[0x7403-0x6c03-1];
154 uint8_t red1;
155 uint8_t f41[0x7803-0x7403-1];
156 uint8_t green1;
157 uint8_t f42[0x7c03-0x7803-1];
158 uint8_t blue1;
159 uint8_t f43[0x8012-0x7c03-1];
160 uint16_t status1; /* Master Status register 0x8012 */
161 uint8_t f44[0xC226-0x8012-2];
162 uint16_t trans; /* Transparency 0xC226 */
163 uint8_t f45[0xC23E -0xC226-2];
164 uint16_t pstop; /* Pace value control 0xc23e */