Lines Matching refs:data
216 pcireg_t data; in glx_pci_read_hook() local
231 data = 0; in glx_pci_read_hook()
235 data = glx_fn0_read(offset); in glx_pci_read_hook()
240 data = glx_fn2_read(offset); in glx_pci_read_hook()
243 data = glx_fn3_read(offset); in glx_pci_read_hook()
246 data = glx_fn4_read(offset); in glx_pci_read_hook()
249 data = glx_fn5_read(offset); in glx_pci_read_hook()
257 return data; in glx_pci_read_hook()
262 int offset, pcireg_t data) in glx_pci_write_hook() argument
273 gen_pci_conf_write(v, tag, offset, data); in glx_pci_write_hook()
280 gen_pci_conf_write(v, tag, offset, data); in glx_pci_write_hook()
286 glx_fn0_write(offset, data); in glx_pci_write_hook()
291 glx_fn2_write(offset, data); in glx_pci_write_hook()
294 glx_fn3_write(offset, data); in glx_pci_write_hook()
297 glx_fn4_write(offset, data); in glx_pci_write_hook()
300 glx_fn5_write(offset, data); in glx_pci_write_hook()
313 pcireg_t data; in glx_get_status() local
315 data = 0; in glx_get_status()
318 data |= PCI_COMMAND_PARITY_ENABLE; in glx_get_status()
319 data |= PCI_STATUS_66MHZ_SUPPORT | in glx_get_status()
322 data |= PCI_STATUS_PARITY_DETECT; in glx_get_status()
324 data |= PCI_STATUS_TARGET_TARGET_ABORT; in glx_get_status()
326 data |= PCI_STATUS_MASTER_TARGET_ABORT; in glx_get_status()
328 data |= PCI_STATUS_MASTER_ABORT; in glx_get_status()
330 return data; in glx_get_status()
361 pcireg_t data; in glx_fn0_read() local
367 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_PCIB); in glx_fn0_read()
370 data = glx_get_status(); in glx_fn0_read()
371 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn0_read()
374 data |= PCI_COMMAND_IO_ENABLE; in glx_fn0_read()
378 data = (PCI_CLASS_BRIDGE << PCI_CLASS_SHIFT) | in glx_fn0_read()
384 data = (0x80 << PCI_HDRTYPE_SHIFT) | in glx_fn0_read()
397 data = 0; in glx_fn0_read()
399 data = pcib_bar_values[index]; in glx_fn0_read()
400 if (data == 0xffffffff) in glx_fn0_read()
401 data = PCI_MAPREG_IO_ADDR_MASK; in glx_fn0_read()
403 data = (pcireg_t)rdmsr(pcib_bar_msr[index]); in glx_fn0_read()
404 data &= ~(pcib_bar_sizes[index] - 1); in glx_fn0_read()
405 if (data != 0) in glx_fn0_read()
406 data |= PCI_MAPREG_TYPE_IO; in glx_fn0_read()
410 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn0_read()
414 data = 0; in glx_fn0_read()
418 return data; in glx_fn0_read()
422 glx_fn0_write(int reg, pcireg_t data) in glx_fn0_write() argument
433 if (data & PCI_COMMAND_IO_ENABLE) in glx_fn0_write()
441 if (data & PCI_COMMAND_PARITY_ENABLE) in glx_fn0_write()
450 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn0_write()
460 if (data == 0xffffffff) { in glx_fn0_write()
461 pcib_bar_values[index] = data; in glx_fn0_write()
463 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_IO) { in glx_fn0_write()
464 data &= PCI_MAPREG_IO_ADDR_MASK; in glx_fn0_write()
465 data &= ~(pcib_bar_sizes[index] - 1); in glx_fn0_write()
467 (0x0000f000ULL << 32) | (1ULL << 32) | data); in glx_fn0_write()
488 pcireg_t data; in glx_fn2_read() local
493 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_IDE); in glx_fn2_read()
496 data = glx_get_status(); in glx_fn2_read()
497 data |= PCI_COMMAND_IO_ENABLE; in glx_fn2_read()
500 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn2_read()
504 data = (PCI_CLASS_MASS_STORAGE << PCI_CLASS_SHIFT) | in glx_fn2_read()
511 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn2_read()
516 data = pciide_bar_value; in glx_fn2_read()
517 if (data == 0xffffffff) in glx_fn2_read()
518 data = PCI_MAPREG_IO_ADDR_MASK & ~(pciide_bar_size - 1); in glx_fn2_read()
521 data = msr & 0xfffffff0; in glx_fn2_read()
523 if (data != 0) in glx_fn2_read()
524 data |= PCI_MAPREG_TYPE_IO; in glx_fn2_read()
528 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn2_read()
535 data = rdmsr(GCSC_IDE_CFG); in glx_fn2_read()
538 data = rdmsr(GCSC_IDE_DTC); in glx_fn2_read()
541 data = rdmsr(GCSC_IDE_ETC); in glx_fn2_read()
545 data = 0; in glx_fn2_read()
549 return data; in glx_fn2_read()
553 glx_fn2_write(int reg, pcireg_t data) in glx_fn2_write() argument
560 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn2_write()
569 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn2_write()
572 if (data == 0xffffffff) { in glx_fn2_write()
573 pciide_bar_value = data; in glx_fn2_write()
575 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_IO) { in glx_fn2_write()
576 data &= PCI_MAPREG_IO_ADDR_MASK; in glx_fn2_write()
577 msr = (uint32_t)data & 0xfffffff0; in glx_fn2_write()
589 wrmsr(GCSC_IDE_CFG, (uint32_t)data); in glx_fn2_write()
592 wrmsr(GCSC_IDE_DTC, (uint32_t)data); in glx_fn2_write()
595 wrmsr(GCSC_IDE_ETC, (uint32_t)data); in glx_fn2_write()
613 pcireg_t data; in glx_fn3_read() local
618 data = PCI_ID_CODE(PCI_VENDOR_AMD, in glx_fn3_read()
622 data = glx_get_status(); in glx_fn3_read()
623 data |= PCI_COMMAND_IO_ENABLE; in glx_fn3_read()
626 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn3_read()
630 data = (PCI_CLASS_MULTIMEDIA << PCI_CLASS_SHIFT) | in glx_fn3_read()
636 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn3_read()
641 data = ac97_bar_value; in glx_fn3_read()
642 if (data == 0xffffffff) in glx_fn3_read()
643 data = PCI_MAPREG_IO_ADDR_MASK & ~(ac97_bar_size - 1); in glx_fn3_read()
646 data = (msr >> 20) & 0x000fffff; in glx_fn3_read()
647 data &= (msr & 0x000fffff); in glx_fn3_read()
649 if (data != 0) in glx_fn3_read()
650 data |= PCI_MAPREG_TYPE_IO; in glx_fn3_read()
653 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn3_read()
657 data = 0; in glx_fn3_read()
661 return data; in glx_fn3_read()
665 glx_fn3_write(int reg, pcireg_t data) in glx_fn3_write() argument
672 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn3_write()
681 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn3_write()
684 if (data == 0xffffffff) { in glx_fn3_write()
685 ac97_bar_value = data; in glx_fn3_write()
687 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_IO) { in glx_fn3_write()
688 data &= PCI_MAPREG_IO_ADDR_MASK; in glx_fn3_write()
692 msr |= ((uint64_t)data & 0xfffff) << 20; in glx_fn3_write()
715 pcireg_t data; in glx_fn4_read() local
720 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_OHCI); in glx_fn4_read()
723 data = glx_get_status(); in glx_fn4_read()
726 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn4_read()
728 data |= PCI_COMMAND_MEM_ENABLE; in glx_fn4_read()
732 data = (PCI_CLASS_SERIALBUS << PCI_CLASS_SHIFT) | in glx_fn4_read()
739 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn4_read()
744 data = ohci_bar_value; in glx_fn4_read()
745 if (data == 0xffffffff) in glx_fn4_read()
746 data = PCI_MAPREG_MEM_ADDR_MASK & ~(ohci_bar_size - 1); in glx_fn4_read()
749 data = msr & 0xffffff00; in glx_fn4_read()
751 if (data != 0) in glx_fn4_read()
752 data |= PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT; in glx_fn4_read()
755 data = 0x40; in glx_fn4_read()
758 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn4_read()
762 data = 0; in glx_fn4_read()
765 data = 0; in glx_fn4_read()
769 return data; in glx_fn4_read()
773 glx_fn4_write(int reg, pcireg_t data) in glx_fn4_write() argument
780 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn4_write()
784 if (data & PCI_COMMAND_MEM_ENABLE) in glx_fn4_write()
793 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn4_write()
796 if (data == 0xffffffff) { in glx_fn4_write()
797 ohci_bar_value = data; in glx_fn4_write()
799 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_MEM) { in glx_fn4_write()
800 data &= PCI_MAPREG_MEM_ADDR_MASK; in glx_fn4_write()
804 msr |= (((uint64_t)data) >> 12) << 20; in glx_fn4_write()
810 msr |= data; in glx_fn4_write()
835 pcireg_t data; in glx_fn5_read() local
840 data = PCI_ID_CODE(PCI_VENDOR_AMD, PCI_PRODUCT_AMD_CS5536_EHCI); in glx_fn5_read()
843 data = glx_get_status(); in glx_fn5_read()
846 data |= PCI_COMMAND_MASTER_ENABLE; in glx_fn5_read()
848 data |= PCI_COMMAND_MEM_ENABLE; in glx_fn5_read()
852 data = (PCI_CLASS_SERIALBUS << PCI_CLASS_SHIFT) | in glx_fn5_read()
859 data = (0x00 << PCI_HDRTYPE_SHIFT) | in glx_fn5_read()
864 data = ehci_bar_value; in glx_fn5_read()
865 if (data == 0xffffffff) in glx_fn5_read()
866 data = PCI_MAPREG_MEM_ADDR_MASK & ~(ehci_bar_size - 1); in glx_fn5_read()
869 data = msr & 0xffffff00; in glx_fn5_read()
871 if (data != 0) in glx_fn5_read()
872 data |= PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT; in glx_fn5_read()
875 data = 0x40; in glx_fn5_read()
878 data = (0x40 << PCI_MAX_LAT_SHIFT) | in glx_fn5_read()
882 data = 0; in glx_fn5_read()
886 data = PCI_USBREV_2_0; in glx_fn5_read()
887 data |= ((msr >> 40) & 0x3f) << 8; /* PCI_EHCI_FLADJ */ in glx_fn5_read()
890 data = 0; in glx_fn5_read()
894 return data; in glx_fn5_read()
898 glx_fn5_write(int reg, pcireg_t data) in glx_fn5_write() argument
905 if (data & PCI_COMMAND_MASTER_ENABLE) in glx_fn5_write()
909 if (data & PCI_COMMAND_MEM_ENABLE) in glx_fn5_write()
918 msr |= ((uint64_t)PCI_LATTIMER(data)) << 32; in glx_fn5_write()
921 if (data == 0xffffffff) { in glx_fn5_write()
922 ehci_bar_value = data; in glx_fn5_write()
924 if (PCI_MAPREG_TYPE(data) == PCI_MAPREG_TYPE_MEM) { in glx_fn5_write()
925 data = PCI_MAPREG_MEM_ADDR(data); in glx_fn5_write()
929 msr |= (((uint64_t)data) >> 12) << 20; in glx_fn5_write()
935 msr |= data; in glx_fn5_write()